An FFS mode array substrate and a manufacturing method thereof are provided. The FFS mode array substrate has: a second insulation layer deposited on a base layer, wherein a first through hole and a second through hole are formed in the second insulation layer; a pixel electrode layer deposited on the second insulation layer, wherein the pixel electrode layer is provided with a plurality of pixel electrodes; and a third insulation layer formed on a source electrode, a drain electrode, the pixel electrodes, and the second insulation layer.

A dual-gate TFT (thin film transistor) array substrate and a manufacturing method thereof are provided. A source electrode and a drain electrode are formed on a common electrode layer; and a common electrode of the common electrode layer, the source electrode and the drain electrode can simultaneously be formed by one mask during manufacturing. Therefore, the dual-gate TFT array substrate and the manufacturing method thereof have beneficial effects to reduce the number of masks, shorten the process, and improve the manufacturing efficiency.

A thin-film transistor substrate constituting a liquid crystal display includes: a thin-film transistor including, a gate electrode, a gate insulating film covering the gate electrode, a semiconductor layer opposing the gate electrode via the gate insulating film, a channel protective film covering the semiconductor layer, a protective film covering over the channel protective film, source and drain electrodes in contact with the semiconductor layer through first contact holes penetrating through the protective film and the channel protective film; a first electrode electrically connected to the drain electrode; a gate wiring extending from the gate electrode; and a source wiring electrically connected to the source electrode. The source wiring and first electrode are respectively electrically connected to the source electrode and drain electrode through respective second contact holes penetrating through the protective film. The first electrode and source wiring have a first transparent conductive film formed on the first insulation film.

The present disclosure discloses a method for preparing electrode including: providing a substrate; forming a buffer layer on the substrate; forming a patterned photoresist on the surface of the buffer layer away from the substrate, the photoresist has a bottom surface and a top surface disposed opposite and a side connected between the bottom surface and the top surface, the bottom surface is bonded to the buffer layer; by dry etching, the portions of the photoresist not covered by the buffer layer is removed to form a receiving area; depositing a conductive film, the conductive film layer includes a waste material forming on the top surface and an electrode filling in the receiving area; and stripping the waste material and the photoresist. The yields of the method for preparing electrode of the present disclosure is high.

A manufacturing method for an array substrate is disclosed. The method includes: forming a gate electrode on a substrate; depositing a gate insulation layer, a semiconductor layer, a source-drain metal layer and a passivation layer on the gate electrode and the substrate, and through a mask process to perform a patterning process to the semiconductor layer, the source-drain metal layer and the passivation layer in order to form a semiconductor pattern, a source-drain pattern and a contact hole pattern; and forming an ITO pixel electrode on the passivation layer and the contact hole pattern. An array substrate is also disclosed. The present invention adopts one mask process to form the semiconductor pattern, the source-drain pattern and the contact hole pattern such that the process of the array substrate is reduced to three masks in order to reduce the manufacturing cost, reduce the operation time and increase the production efficiency.

A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween; an interlayer insulating layer on the semiconductor member; a data conductor on the interlayer insulating layer; and a passivation layer on the data conductor, wherein the interlayer insulating layer has a first hole on the channel region.

A thin film transistor “TFT”) substrate includes a substrate, an active layer over the substrate, and first and second TFTs over the substrate. The active layer includes: a first drain region, a first channel region and a first source region, which function as a drain, a channel and a source of the first TFT: a first lightly doped region between the first drain region and the first channel region: a second lightly doped region between the first channel region and the first source region: and a second drain region, a second channel region and a second source region, which function as a drain, a channel and a source of the second TFT. An impurity concentration at the second drain or source region is lower than an impurity concentration at the first drain or source region and higher than an impurity concentration at the first or second channel region.

A method for preparing an array substrate, a display panel and an evaporation apparatus are disclosed. A method comprises: fixing a base substrate to an evaporation stage; attaching at least one shielding sheet to the base substrate to cover at least a preset area of the base substrate; arranging and aligning an open mask in association with the base substrate, wherein the open mask has at least one opening for vapor deposition, and the at least one shielding sheet is positioned corresponding to the at least one opening and each has an area that is less than an area of a corresponding opening to shield a portion of the corresponding opening, and wherein the portion of the corresponding opening is separate from a boundary of the corresponding opening; and evaporating to form an evaporation material layer on the base substrate, to which the shielding sheet is attached.

A method for forming a mask pattern is provided, comprising forming a negative photoresist on a substrate; in an environment without oxygen, to performing a first exposure on the negative photoresist by use of a first ordinary mask plate, so that a fully-cured portion of the negative photoresist is exposed to light and a semi-cured portion and a removed portion of the negative photoresist are not exposed to light; in an environment with oxygen, performing a second exposure on the negative photoresist by use of a second ordinary mask plate, so that the semi-cured portion of the negative photoresist is exposed to light and the removed portion of the negative photoresist not exposed to light; removing the uncured negative photoresist and forming the mask pattern.

A display device includes: a base substrate comprising a first light blocking area extending in a first direction, a second light blocking area extending in a second direction intersecting the first direction and a light transmitting area defined by the first light blocking area and the second light blocking area; a gate line on the base substrate at the first light blocking area; a data line on the base substrate at the second light blocking area; a thin film transistor connected to the gate line and the data line; a protective layer on the thin film transistor; a black matrix on the protective layer at at least one of the first light blocking area and the second light blocking area; and a pixel electrode connected to the thin film transistor through a contact hole defined in the protective layer and the black matrix.