An organic light-emitting diode display including a substrate, a first transistor, and an organic light-emitting element. The first transistor is positioned on the substrate. The first transistor includes a first active layer including a first source region, a first channel region extending from the first source region, a first drain region extending from the first channel region, a first conductive pattern, and a first gate electrode positioned on the first active layer. The organic light-emitting element is connected to the first transistor. The first conductive pattern is in contact with the first active layer and covers the first source region and the second source region.

A semiconductor device is fabricated by a method including the following steps: a first step of forming a semiconductor film containing a metal oxide over an insulating layer; a second step of forming a conductive film over the semiconductor film; a third step of forming a first resist mask over the conductive film and etching the conductive film to form a first conductive layer and to expose a top surface of the semiconductor film that is not covered with the first conductive layer; and a fourth step of forming a second resist mask that covers a top surface and a side surface of the first conductive layer and part of the top surface of the semiconductor film and etching the semiconductor film to form a semiconductor layer and to expose a top surface of the insulating layer that is not covered with the semiconductor layer.

A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

The present disclosure relates to a method of manufacturing a thin film device. A multilevel nanoimprint lithography template is transferred into a thin film stack comprising an electrode layer and a blanket sacrificial layer covering the electrode layer. The template is transferred, thereby patterning the device and exposing a predefined insulating area of the electrode while keeping a remaining portion of the sacrificial layer that covers a pre-defined electrical contact area of the electrode. An area selective atomic layer deposition (ALD) process is performed to selectively cover the exposed area of the electrode layer with a cover layer. After removing the remaining portion of the sacrificial layer the electrical contact area of the electrode layer is exposed for further processing.

A substrate including a first signal line and a first electrode disposed on the substrate, an oxide semiconductor layer pattern overlapping the first electrode, an insulating layer disposed between the first electrode and the oxide semiconductor layer pattern, a second signal line intersecting the first signal line, a second electrode electrically connected to the oxide semiconductor layer pattern, a third electrode electrically connected to the oxide semiconductor layer pattern and spaced apart from the second electrode, and an insulator comprising a first portion disposed between the first signal line and the second signal line, and at least partially overlapping with both of the first signal line and the second signal line.

A display device is provided. The display device includes a base; a gate conductor disposed directly on the base and including a gate line and a gate electrode; a gate insulating layer disposed on the gate conductor and including an overlap portion, which overlaps with the gate conductor, and a non-overlap portion, which is connected to the overlap portion, does not overlap with the gate conductor, and is spaced apart from the base; and a semiconductor pattern disposed on the gate insulating layer and overlapping with the gate electrode, wherein edges of the gate insulating layer project further than edges of the gate conductor and edges of the semiconductor pattern.

A method for manufacturing an active matrix substrate includes: (A) a step of forming a laminated film including a lower conductive film, a lower insulating film, and a semiconductor film in this order on a substrate; (B) a step of forming a first resist layer; (C) a step of performing a patterning on the laminated film, the step including, in the first formation region, forming the first substructure including a first lower conductive layer, a first lower insulating layer, and a first semiconductor layer respectively formed from the lower conductive film, the lower insulating film, and the semiconductor film, and (D) a step of forming source and drain electrodes electrically connected to the first semiconductor layer.

A method for manufacturing an array substrate comprises forming a pattern including an active layer, a gate insulating layer and a gate on a base substrate, and forming a pattern including an interlayer dielectric layer, a source, a drain and a pixel electrode through a single patterning process on the base substrate formed with the pattern of the active layer, the gate insulating layer and the gate. An array substrate and a display device are further provided.

An array substrate and a fabrication method thereof, and a display device are provided. The array substrate includes a base substrate and a peripheral lead, a ground signal terminal, a conductive adhesive, and a barrier wall structure located on the base substrate, wherein, the conductive adhesive is connected with the ground signal terminal, and the barrier wall structure is located between the peripheral lead and the ground signal terminal, and configured for blocking the conductive adhesive from diffusing toward the peripheral lead.

A gate unit and a manufacturing method thereof, a method of manufacturing an array substrate, and a display mechanism are provided. The method of manufacturing a gate unit includes: providing a conductive layer on a substrate; forming a photoresist layer on a side of the conductive layer away from the substrate; exposing the photoresist layer, and then developing the photoresist layer to form a groove extending through the photoresist layer on the photoresist layer, so as to form the photoresist layer with a pattern; and electrochemically depositing a functional material on the photoresist layer with the pattern, and then removing the photoresist layer to obtain the conductive layer having a pattern layer formed thereon, so as to obtain the gate unit.