A photomask, a method of manufacturing an array substrate, and a display panel are provided. The photomask includes a photomask line of a first conductive portion, a photomask line of a second conductive portion spaced apart from the photomask line of the first conductive portion, and a bridging line. Two opposite ends of the bridging line are respectively connected to the photomask line of the first conductive portion and the photomask line of the second conductive portion, and a width of the bridging line is less than a preset width.

An array substrate, a display panel, and an electronic device are provided. The array substrate includes: a base substrate; a first electrode arranged on the base substrate; a gate line arranged on the base substrate, wherein the gate line is electrically insulated from the first electrode; a second electrode arranged on a side of the gate line away from the base substrate, wherein at least one first sub-pixel unit provided on the base substrate includes: a first connection portion arranged in a same layer as the second electrode and a second connection portion arranged in a same layer as the gate line, wherein the second connection portion is electrically connected to the first electrode, and an orthographic projection of the second connection portion on the base substrate at least partially overlaps an orthographic projection of the first connection portion on the base substrate.

The present disclosure provides a positive photoresist composition including a major adhesive material and a photosensitizer, wherein the photoresist composition further includes a photoisomerizable compound which would be converted into an ionic structure with an increased degree of molecular polarity after ultraviolet irradiation. The formation of the ionic structure with increased polarity of the molecule reduces the adhesion between the positive photoresist and the organic film layer, facilitates stripping after formation of the via, and improves the product rate of pass. Further, the present disclosure provides a via-forming method using the positive resist composition, a display substrate including the via formed by the via-forming method, and a display device including the display substrate.

A display panel and method of manufacturing the same are provided. The method of manufacturing the display panel includes the steps of providing a substrate, forming a gate on the substrate, forming a gate insulating layer on the gate and the substrate, forming a polysilicon layer on the gate insulating layer, performing a first gray-scale mask process on the polysilicon layer to form a source region, a drain region and an active region located between the source region and the drain region by the polysilicon layer, forming an interlayer dielectric layer on the gate insulating layer and the polysilicon layer, forming a first electrode layer on the interlayer dielectric layer, performing a second gray-scale mask process on the first electrode layer and the interlayer dielectric layer.

A manufacturing method of a low temperature poly-silicon (LTPS) array substrate is described. The LTPS array substrate includes a metal light-shielding layer, a buffer layer, a polycrystalline silicon layer, a gate insulating and interlayer insulating layer, a gate line layer, and a source and drain electrode layer. The method adopts a one-time chemical vapor deposition process to form a gate insulator and interlayer insulating layer. A gate line trench is formed in the gate insulating layer and the interlayer insulating layer, thereby reducing the thickness of the LTPS array substrate film layer and the process steps.

Disclosed is a display apparatus and a method for manufacturing the same, wherein the display apparatus comprises a substrate, a light shielding layer, a signal line and a first electrode on the substrate, an active layer, a gate electrode, a second electrode, a first connection electrode for connecting the active layer with the signal line, and a second connection electrode for connecting the active layer with any one of the first electrode and the second electrode, wherein any one of the first electrode and the second electrode is a pixel electrode of a display device, and the other is a common electrode of the display device, the light shielding layer, the signal line and the first electrode are disposed on the same layer, and the first connection electrode and the second connection electrode are formed of the same material as that of the second electrode.

The application discloses a method adapted to manufacture an array substrate and a display panel. The method includes: form a photoresist layer, a source and a drain; post-baking the photoresist layer, so that the photoresist layer flows to the position of a channel; etching a semiconductor layer to obtain a preset pattern; and peeling off the photoresist layer.

The present application relates to the field of display technology and, in particular, to an array substrate, a manufacturing method of the array substrate, and a display device. An array substrate comprises: a base substrate having a pixel display area and a gate drive circuit area; a first thin film transistor formed in the pixel display area, the first thin film transistor comprising a first gate insulating layer; a second thin film transistor formed in the gate drive circuit area, the second thin film transistor comprising a second gate insulating layer, where a thickness of the second gate insulating layer is smaller than a thickness of the first gate insulating layer.

A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed. In an embodiment, the method may include depositing a first buffer layer over a substrate; depositing a first channel layer over the first buffer layer; depositing a second buffer layer over the first channel layer; depositing a second channel layer over the second buffer layer; depositing a third buffer layer over the second channel layer; etching the first buffer layer, the first channel layer, the second buffer layer, the second channel layer, and the third buffer layer to form a fin structure; etching the first buffer layer, the second buffer layer, and the third buffer layer to form a first plurality of openings; forming a first gate stack in the first opening disposed in the first buffer layer, a second gate stack in the first opening disposed in the second buffer layer, and a third gate stack in the first opening disposed in the third buffer layer; and replacing the second buffer layer and a portion of the second gate stack with an isolation structure.

A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.