An array substrate, a method for fabricating the same, and a display panel are provided. The array substrate includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer. The first metal layer includes a first data line and a first vertical scan line. The second metal layer includes a horizontal scan line. The third metal layer includes a second data line and a second vertical scan line. The second data line is connected to the first data line through a first via hole. The second vertical scan line is connected to the first vertical scan line through a second via hole. The second vertical scan line is connected to the horizontal scan line through a third via hole. The first via hole, the second via hole, and the third via hole are formed by a same manufacturing process.

Disclosed are a method for manufacturing an array substrate, an array substrate and a display device. The method includes the following operations: sequentially forming a gate, a gate insulation layer, an active layer, an ohmic contact layer and a metal layer on a base substrate; forming a photolithography mask on the metal layer, a thickness of the photolithography mask being between 1.7 μm and 1.8 μm; exposing the photolithography mask through a mask plate to make a uniformity of the photolithography mask in a half-exposed area of the mask plate reach a preset uniformity; and manufacturing the array substrate based on the exposed photolithography mask.

An array substrate, a method of manufacturing the same, and a display panel are disclosed. The method includes: providing a substrate; depositing a light-shielding material on the substrate; and etching the light-shielding material to form a light-shielding layer, where an included angle formed between a side surface of the formed light-shielding layer and a plane where the substrate is located lies in the range of 80 to 110 degrees.

Disclosed is a display device that with low power consumption. The display device includes a first thin film transistor having a polycrystalline semiconductor layer in an active area and a second thin film transistor having an oxide semiconductor layer in the active area, wherein at least one opening disposed in a bending area has the same depth as one of a plurality of contact holes disposed in the active area, whereby the opening and the contact holes are formed through the same process, and the process is therefore simplified, and wherein a high-potential supply line and a low-potential supply line are disposed so as to be spaced apart from each other in the horizontal direction, whereas a reference line and the low-potential supply line are disposed so as to overlap each other, thereby preventing signal lines from being shorted.

A display apparatus is disclosed that includes contact holes formed to expose at least a portion of a conductive layer or a semiconductor layer without damage to the surface of the conductive layer or the semiconductor layer, and a method of manufacturing the display apparatus. The display apparatus includes a substrate, a conductive mound arranged on the substrate, a first insulating mound arranged on the substrate, and a semiconductor layer including a first region arranged on the conductive mound, and a second region arranged on the first insulating mound. The second region of the semiconductor layer substantially covers an upper surface of the first insulating mound.

A thin film transistor panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate and including a first semiconductor layer including a low temperature polysilicon and a first control electrode overlapping the first semiconductor layer; a second transistor disposed on the substrate and including a second semiconductor layer including an oxide semiconductor and a second control electrode overlapping the second semiconductor layer; a first gate insulation layer disposed between the first semiconductor layer and the first control electrode of the first transistor and including a first insulation layer and a second insulation layer; and a second gate insulation layer disposed between the second semiconductor layer and the second control electrode of the second transistor and including the second insulation layer, wherein the density of the first insulation layer may be higher than the density of the second insulation layer, the first semiconductor layer of the first transistor may be in contact with the first insulation layer, and the second semiconductor layer of the second transistor may be in contact with the second insulation layer.

This disclosure provides an array substrate and its preparation method, a display panel and a display device, belonging to the display technical field. The array substrate includes a test unit area and a terminal area. The test unit area includes a first metal layer having a first flat layer thereon. Each of input and output terminals in the terminal area structurally includes a second metal layer and a third metal layer on a side of the second metal layer away from the substrate. A second flat layer covering edges of the third metal layer is on the third metal layer. In a thickness direction of the substrate, a surface of the first flat layer away from the substrate is not higher than that of the second flat layer away from the substrate. When the driving chip is bound, effective lapping joint and normal driving of the display panel is ensured.

A half via hole structure, a method for manufacturing the same, an array substrate, and a display panel are provided. The half via hole structure includes: a spacer layer arranged on an underlaying substrate; a passivation layer arranged on the spacer layer and provided with a first via hole, an orthographic projection of the first via hole on the underlaying substrate being within that of the spacer layer on the underlaying substrate; a first conductive layer arranged on the spacer layer and having a width smaller than a diameter of the first via hole; an insulating layer arranged between the spacer layer and the passivation layer and provided with a second via hole; and a second conductive layer arranged on the passivation layer and overlapped with the first conductive layer through the first via hole.

In a TFT layer forming step, first, a semiconductor layer on a resin substrate is formed by performing a semiconductor layer forming step, and subsequently a gate insulating film is formed to cover the semiconductor layer by performing a gate insulating film forming step, and then a first metal layer is formed by performing a first metal film deposition step, a first photo step, and a first etching step, and a second metal layer is formed by performing a second metal film deposition step, a second photo step, and a second etching step, thereby forming a gate layer in which the first metal layer and the second metal layer are layered.

A self-aligned short-channel SASC electronic device includes a first semiconductor layer formed on a substrate; a first metal layer formed on a first portion of the first semiconductor layer; a first dielectric layer formed on the first metal layer and extended with a dielectric extension on a second portion of the first semiconductor layer that extends from the first portion of the first semiconductor layer, the dielectric extension defining a channel length of a channel in the first semiconductor layer; and a gate electrode formed on the substrate and capacitively coupled with the channel. The dielectric extension is conformally grown on the first semiconductor layer in a self-aligned manner. The channel length is less than about 800 nm, preferably, less than about 200 nm, more preferably, about 135 nm.