The present disclosure provides a transistor device, a manufacturing method thereof, a display substrate and a display device. The transistor device includes a base substrate, as well as a first transistor and a second transistor that are disposed on the base substrate. The first transistor includes a first active layer. The second transistor includes a second gate. The first active layer and the second gate are disposed in the same layer.

A transistor substrate includes a substrate, a semiconductor layer overlapping the substrate, and a gate electrode overlapping the semiconductor layer. The semiconductor layer includes a channel unit, a conductive unit directly connected to an end of the channel unit, and an edge unit positioned at an edge of the conductive unit. A carbon concentration of the edge unit is higher than each of a carbon concentration of the channel unit and a carbon concentration of the conductive unit.

A display device includes a first conductive layer including a first voltage line and a second voltage line, a buffer layer, a semiconductor layer including a first active layer and a second active layer, a first gate insulating layer, a second conductive layer including a first gate electrode overlapping the first active layer and a second gate electrode overlapping the second active layer, a passivation layer, a via layer, a bank pattern layer including a first bank pattern and a second bank pattern partially spaced apart from each other, a third conductive layer including a first electrode and a second electrode spaced apart from each other, and light emitting elements. The passivation layer includes silicon nitride (SiN.sub.x), and a ratio of a number of silicon-hydrogen bonds (Si—H) to a number of nitrogen-hydrogen bonds (N—H) in the silicon nitride (SiN.sub.x) is in a range of about 1:0.6 to about 1:1.5.

A display panel includes a base, at least one separation pillar, at least one protection pattern, and a light-emitting functional layer. The at least one separation pillar is disposed in the isolation region on the base, each separation pillar is disposed around the opening region, and a longitudinal section of the separation pillar perpendicular to an extending direction of the separation pillar is I-shaped. The at least one protection pattern is disposed on a surface of at least one separation pillar facing away from the base. The light-emitting functional layer is disposed at least in both the pixel region and the isolation region on a surface of the at least one protection pattern facing away from the base, wherein the light-emitting functional layer is disconnected at an inner side face and an outer side face of the separation pillar.

An array substrate and a method for manufacturing the same, and a display device are provided. The array substrate includes a base substrate and the array substrate includes a plurality of pixel units. In each of the plurality of pixel units, the array substrate includes a thin film transistor and a storage capacitor disposed above the base substrate, the storage capacitor includes a metal layer, an intermediate layer, and a reflective layer disposed in a stacked manner, the metal layer being adjacent to the base substrate. The array substrate further includes a common electrode layer disposed on a side of the storage capacitor facing away from the base substrate, the reflective layer is electrically connected to the common electrode layer, and the metal layer is electrically connected to an active layer of the thin film transistor.

A display device includes a pixel circuit, a first insulating layer covering the pixel circuit, a first electrode disposed on the first insulating layer, a second electrode disposed on the first insulating layer and spaced apart from the first electrode in a first direction, and a light emitting element electrically connected to the first electrode and the second electrode and disposed between the first electrode and the second electrode. A recess is provided in a first region of the first insulating layer between the first electrode and the second electrode when viewed in a plan view, and a width of the recess in the first direction is greater than a length of the light emitting element in the first direction. The first electrode and the second electrode do not overlap the recess when viewed in a plan view.

A display substrate, a method for forming the display substrate and a display device are provided. The display substrate includes: a first conductive pattern located on a base substrate, where a ring-shaped conductive protection structure is arranged at an edge of a preset region of the first conductive pattern and surrounds the preset region, and the conductive protection structure is made of an anti-dry-etching material; an insulation layer covering the first conductive pattern; and a second conductive pattern located on a side of the insulation layer away from the first conductive pattern, where the second conductive pattern is electrically connected to the first conductive pattern through the via-hole.

A photopolymerizable resin composition includes a first layer and a second layer; and a barrier layer disposed between the first layer and the second layer, the barrier layer includes one or more of SiNx, SiOx, SiON, Mo, a Mo oxide, Cu, a Cu oxide, Al, an Al oxide, Ag, and a Ag oxide.

A display device and a method of driving a display device are provided. A display device includes a substrate, a first conductive layer on the substrate and including a lower light blocking pattern, a buffer layer on the first conductive layer, a semiconductor layer including a semiconductor pattern on the buffer layer, a gate insulating layer on the semiconductor pattern, a second conductive layer including a gate electrode on the gate insulating layer, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including a first conductive pattern electrically coupling the lower light blocking pattern to the semiconductor pattern, wherein the first conductive pattern is coupled to the lower light blocking pattern through a first contact hole passing through the planarization layer and the buffer layer, and coupled to the semiconductor pattern through a second contact hole passing through the planarization layer.

The present disclosure provides an array substrate and a manufacturing method of the array substrate. In the manufacturing method of the array substrate, during performing a first wet etching and a second wet etching on a second metal layer, the wet etching is stopped when a copper conductive layer is merely etched completely. Because a wet etching speed of a liner layer is slow, an etching time of the wet etching and a CD loss of the copper conductive layer can be greatly reduced, and the CD loss is relatively small. Meanwhile, an entire CD loss of the second metal layer can be reduced, and an aperture ratio can be improved.