A semiconductor device, including a semiconductor layer of a first conductivity type, having a main surface with a diode trench formed therein, an inner wall insulating film, including a side wall insulating film, formed along side walls of the diode trench, and a bottom wall insulating film, formed along a bottom wall of the diode trench and having a thickness greater than a thickness of the side wall insulating film, and a bidirectional Zener diode, formed on the bottom wall insulating film inside the diode trench and having a pair of first conductivity type portions and at least one second conductivity type portion formed between the pair of first conductivity type portions.

A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

A GaN-based superjunction vertical power transistor and a manufacturing method thereof. The transistor includes: a N.sup.−-GaN layer; a first P-GaN layer as a current blocking layer, formed on the N.sup.−-GaN layer and having a gate region window; and a thin barrier Al(In, Ga)N/GaN heterostructure conformally formed on the current blocking layer and filling the bottom and one or more sidewalls of the gate region window, wherein the N.sup.−-GaN layer has an etched groove completely or partially filled with a second P-type GaN layer, an N.sup.+-GaN layer is formed under the second P-type GaN layer, and the N.sup.+-GaN layer is in direct contact with the second P-type GaN layer and the N.sup.−-GaN layer to form a superjunction composite structure.

The present application provides a semiconductor structure and a method for manufacturing the same, which solves a problem that an existing semiconductor structure is difficult to deplete a carrier concentration of a channel under a gate to realize an enhancement mode device. The semiconductor structure includes: a channel layer and a barrier layer superimposed in sequence, wherein a gate region is defined on a surface of the barrier layer; a plurality of trenches formed in the gate region, wherein the plurality of trenches extend into the channel layer; and a P-type semiconductor material filling the plurality of trenches.

A main Insulated Gate Bipolar Transistor (IGBT) and a sense IGBT may have a sense resistor connected between a sense emitter of the sense IGBT and a main emitter of the main IGBT. Back-to-back Zener diodes may be connected between a sense gate of the sense IGBT and the sense emitter, and configured to clamp a voltage between the sense gate and the sense emitter during an electrostatic discharge (ESD) event.

Described herein are the design and fabrication of Group III trioxides, such as β-Ga.sub.2O.sub.3, trench-MOS barrier Schottky (TMBS) structures with high voltage (>1 kV), low leakage capabilities, while addressing on the necessary methods to meet the re-quirements unique to Group III trioxides, such as β-Ga.sub.2O.sub.3.

Disclosed are an enhancement-mode device and a preparation method therefor. The enhancement-mode device adopts a vertical or semi-vertical structure, and a nitride heterojunction with a non-polar surface or semi-polar face is prepared, such that two-dimensional electron gas is interrupted at the position, and the enhancement-mode device is obtained.

An interlayer film is deposited on a device layer on a substrate. A contact layer is deposited on the interlayer film. The interlayer film has a broken bandgap alignment to the device layer to reduce a contact resistance of the contact layer to the device layer.

A semiconductor device is disclosed including a semiconductor layer, a first well doped with dopants of a first conductivity type defined in the semiconductor layer, a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the semiconductor layer adjacent the first well to define a PN junction between the first and second wells, and an isolation structure positioned in the second well. The semiconductor device also includes a first source/drain region positioned in the first well, a second source/drain region positioned in the second well adjacent a first side of the isolation structure, a doped region positioned in the second well adjacent a second side of the isolation structure, and a gate structure positioned above the semiconductor layer, wherein the gate structure vertically overlaps a portion of the doped region.

Existing semiconductor transistor processes may be leveraged to form lateral extensions adjacent to a conventional gate structure. The dielectric thickness under these lateral gate extensions can be varied to tune RF switch FET device performance and enable resistance to breakdown at high operating voltages. These extensions may be patterned with dimensions that are not limited by lithographic resolution and overlay capabilities and are compatible with conventional processing for ease of integration with other devices. The lateral extensions and dielectric spacers may be used to form self-aligned source, drain, and channel regions. A thick dielectric layer may be formed under a narrow extension gate to improve operation voltage range. The present invention provides an innovative structure with lateral gate extensions which may be referred to as EGMOS (extended gate metal oxide semiconductor).