A device including a III-N material is described. The device includes a transistor structure having a first layer including a first group III-nitride (III-N) material, a polarization charge inducing layer above the first layer, the polarization charge inducing layer including a second III-N material, a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The device further includes a plurality of peripheral structures adjacent to transistor structure, where each of the peripheral structure includes the first layer, but lacks the polarization charge inducing layer, an insulating layer above the peripheral structure and the transistor structure, wherein the insulating layer includes a first dielectric material. A metallization structure, above the peripheral structure, is coupled to the transistor structure.

A vertical high-blocking III-V bipolar transistor, which includes an emitter, a base and a collector. The emitter has a highly doped emitter semiconductor contact region of a first conductivity type and a first lattice constant. The base has a low-doped base semiconductor region of a second conductivity type and the first lattice constant. The collector has a layered low-doped collector semiconductor region of the first conductivity type with a layer thickness greater than 10 μm and the first lattice constant. The collector has a layered highly doped collector semiconductor contact region of the first conductivity type. A first metallic connecting contact layer is formed in regions being integrally connected to the emitter. A second metallic connecting contact layer is formed in regions being integrally connected to the base. A third metallic connecting contact region is formed at least in regions being arranged beneath the collector.

A vertical high-blocking III-V bipolar transistor, which includes an emitter, a base and a collector. The emitter has a highly doped emitter semiconductor contact region of a first conductivity type and a first lattice constant. The base has a low-doped base semiconductor region of a second conductivity type and the first lattice constant. The collector has a layered low-doped collector semiconductor region of the first conductivity type with a layer thickness greater than 10 μm and the first lattice constant. The collector has a layered highly doped collector semiconductor contact region of the first conductivity type. A first metallic connecting contact layer is formed in regions being integrally connected to the emitter. A second metallic connecting contact layer is formed in regions being integrally connected to the base. A third metallic connecting contact region is formed at least in regions being arranged beneath the collector.

A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer.

A high electron mobility transistor (HEMT) made of primarily nitride semiconductor materials is disclosed. The HEMT, which is a type of reverse HEMT, includes, on a C-polar surface of a SiC substrate, a barrier layer and a channel layer each having N-polar surfaces in respective top surfaces thereof. The HEMT further includes an intermediate layer highly doped with impurities and a Schottky barrier layer on the channel layer. The Schottky barrier layer and a portion of the intermediate layer are removed in portions beneath non-rectifying electrodes but a gate electrode is provided on the Schottky barrier layer.

The present disclosure provides a nitride semiconductor device. The nitride semiconductor device includes: an electron transport layer, made of a nitride semiconductor; an electron supply layer, disposed on the electron transport layer and made of a nitride semiconductor having a band gap greater than a band gap of the nitride semiconductor of the electron transport layer; a first protective layer, disposed on the electron supply layer and made of a nitride semiconductor having a band gap less than the band gap of the nitride semiconductor of the electron supply layer; a second protective layer, disposed on a portion of the first protective layer and made of a nitride semiconductor having a band gap greater than the band gap of the nitride semiconductor of the first protective layer; and a gate layer, disposed on the second protective layer.

The present disclosure provides a nitride semiconductor device. The nitride semiconductor device includes: an electron transport layer, made of a nitride semiconductor; an electron supply layer, disposed on the electron transport layer and made of a nitride semiconductor having a band gap greater than a band gap of the nitride semiconductor of the electron transport layer; a first protective layer, disposed on the electron supply layer and made of a nitride semiconductor having a band gap less than the band gap of the nitride semiconductor of the electron supply layer; a second protective layer, disposed on a portion of the first protective layer and made of a nitride semiconductor having a band gap greater than the band gap of the nitride semiconductor of the first protective layer; and a gate layer, disposed on the second protective layer.

The present disclosure is directed to controlling charge transfer in 2D materials. A charge-transfer controlled 2D device comprises a 2D active conducting material, a 2D charge transfer source material, and at least one overlapping portion wherein the 2D active conducting material overlaps the 2D charge transfer source material including at least one edge of the 2D charge transfer source material.

The present disclosure is directed to controlling charge transfer in 2D materials. A charge-transfer controlled 2D device comprises a 2D active conducting material, a 2D charge transfer source material, and at least one overlapping portion wherein the 2D active conducting material overlaps the 2D charge transfer source material including at least one edge of the 2D charge transfer source material.

A method is provided for forming Group IIIA-nitride layers, such as GaN, on substrates. The Group IIIA-nitride layers may be deposited on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates. The Group IIIA-nitride layers may be deposited by heteroepitaxial deposition on mesa-patterned semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) substrates.