Preparation method for platform-shaped active region based P-I-N diode string in reconfigurable loop antenna

Abstract

A preparation method for a platform-shaped active region based P-I-N diode string in a reconfigurable loop antenna includes: (a) selecting an SOI substrate; (b) etching the SOI substrate to form a platform-shaped active region; (c) depositing a P-type Si material and an N-type Si material around the platform-shaped active region by an in-situ doping process to form a P region and an N region respectively; (d) depositing a polysilicon material around the platform-shaped active region; (e) forming leads on a surface of the polysilicon material and forming PADs by photolithography, to form the P-I-N diode string. Therefore, a high-performance platform-shaped active region based P-I-N diode string suitable for a solid-state plasma antenna can be provided by an in-situ doping process.

Claims

1. A preparation method for a platform-shaped active region based P-I-N diode string in a reconfigurable loop antenna, wherein the P-I-N diode string is configured for manufacturing the reconfigurable loop antenna, and the reconfigurable loop antenna comprises: a semiconductor substrate; a dielectric plate; a first P-I-N diode ring, a second P-I-N diode ring, first direct current (DC) bias wires and second DC bias wires, all disposed on the semiconductor substrate; and a coupling type feed source, disposed on the dielectric plate; wherein the preparation method comprises steps of: (a) selecting a silicon-on-insulator (SOI) substrate; (b) etching the SOI substrate to form a platform-shaped active region; (c) depositing a P-type silicon material and an N-type silicon material around the platform-shaped active region by an in-situ doping process to form a P region and an N region respectively, wherein an I region transversely located between the P region and the N region is formed in a top silicon layer of the SOI substrate; (d) depositing a polysilicon material around the platform-shaped active region by a chemical vapor deposition (CVD) process; (e) depositing a fourth protective layer on a surface of the SOI substrate by a CVD process; (f) activating impurities in the P region and N region by an annealing process; and (g) forming leads on a surface of the polysilicon material and forming PADs by photolithography, to obtain the P-I-N diode string.

2. The preparation method according to claim 1, wherein the step (b) comprises: (b1) forming a first protective layer on a surface of the SOI substrate by a CVD process; (b2) forming an active region pattern on the first protective layer by a photolithography process using a first mask; (b3) etching the first protective layer and the top silicon layer of the SOI substrate in designated positions around the active region pattern by a dry etching process.

3. The preparation method according to claim 1, after the step (b), further comprising: (x1) oxidizing sidewalls of the platform-shaped active region by an oxidizing process to form an oxide layer on the sidewalls of the platform-shaped active region; and (x2) etching off the oxide layer by a wet etching process to planarize the sidewalls of the platform-shaped active region.

4. The preparation method according to claim 1, wherein the step (c) comprises: (c1) depositing a second protective layer on a surface of the SOI substrate; (c2) forming a P region pattern on a surface of the second protective layer by a photolithography process using a second mask; (c3) removing the second protective layer on the P region pattern by a wet etching process; (c4) depositing the P-type silicon material on a sidewall of the platform-shaped active region to form the P region by the in-situ doping process; (c5) depositing a third protective layer on a surface of the SOI substrate; (c6) forming an N region pattern on a surface of the third protective layer by a photolithography process using a third mask; (c7) removing the third protective layer on the N region pattern by a wet etching process; and (c8) depositing the N-type silicon material on another sidewall of the platform-shaped active region to form the N region by the in-situ doping process.

5. The preparation method according to claim 4, wherein the step (c4) comprises: (c41) depositing the P-type silicon material on the sidewall of the platform-shaped active region by the in-situ doping process; (c42) etching the P-type silicon material by a dry etching process using a fourth mask to form the P region on the sidewall of the platform-shaped active region; and (c43) removing the second protective layer on the surface of the SOI substrate by a selective etching process.

6. The preparation method according to claim 4, wherein the step (c8) comprises: (c81) depositing the N-type Si material on the another sidewall of the platform-shaped active region by the in-situ doping process; (c82) etching the N-type silicon material by a dry etching process using a fifth mask to form the N region on the another sidewall of the platform-shaped active region; and (c83) removing the third protective layer on the surface of the SOI substrate by a selective etching process.

7. The preparation method according to claim 1, wherein the step (g) comprises: (g1) forming a lead hole pattern on a surface of the fourth protective layer by a photolithography process using a sixth mask; (g2) etching the fourth protective layer to expose a part of the polysilicon material by an anisotropic etching process to form the lead holes; (g3) sputtering a metal material into the lead holes to form a metal silicide; and (g4) performing a passivation treatment, forming PADs by photolithography and performing an interconnection, to obtain the P-I-N diode string.

8. The preparation method according to claim 1, wherein the first plasma P-I-N diode ring comprises a first plasma P-I-N diode string, the second plasma P-I-N diode ring comprises a second plasma P-I-N diode string, and a perimeter of each of the first plasma P-I-N diode ring and the second plasma P-I-N diode ring is equal to an electromagnetic wavelength of a signal to be received.

9. The preparation method according to claim 8, wherein the first DC bias wires are disposed on two ends of the first plasma P-I-N diode string, the second DC bias wires are disposed on two ends of the second plasma P-I-N diode string, and the first DC bias wires and the second DC bias wires are formed on the semiconductor substrate by a heavily doped polysilicon.

10. The preparation method according to claim 1, wherein the coupling type feed source is mounted on the dielectric plate; the dielectric plate is provided with a metal microstrip patch on an upper surface and a metal grounding plate on a lower surface; and the metal microstrip patch comprises a main branch, first sub-branches and second sub-branches.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Specific embodiments of the disclosure are explained in detail with reference to accompanying drawings.

(2) FIG. 1 is a structural schematic view of a reconfigurable loop antenna according to an embodiment of the disclosure.

(3) FIG. 2 is a flowchart of a preparation method for a platform-shaped active region based P-I-N diode string in a reconfigurable loop antenna according to an embodiment of the disclosure.

(4) FIG. 3 is a structural schematic view of a semiconductor substrate of a reconfigurable loop antenna provided by an embodiment of the disclosure.

(5) FIG. 4 is a structural schematic view of a dielectric plate of a loop antenna provided by an embodiment of the disclosure.

(6) FIG. 5 is a structural schematic view of a P-I-N diode in a reconfigurable loop antenna provided by an embodiment of the disclosure.

(7) FIG. 6 is a structural schematic view of a P-I-N diode string in a reconfigurable loop antenna provided by an embodiment of the disclosure.

(8) FIGS. 7A to 7S are schematic views of another preparation method for a platform-shaped active region based P-I-N diode in a reconfigurable loop antenna according to an embodiment of the disclosure.

(9) FIG. 8 is a structural schematic view of another platform-shaped active region based P-I-N diode in a reconfigurable loop antenna according to an embodiment of the disclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(10) In order to make the objectives, features and advantages of the disclosure more apparent and easy to understand, specific embodiments of the disclosure are explained in detail with reference to accompanying drawings.

(11) The disclosure provides a preparation method for a platform-shaped active region based P-I-N diode suitable for forming a reconfigurable loop antenna. The P-I-N diode may be a transverse P-I-N diode formed based on a silicon-on-insulator (SOI), and when a DC bias voltage is applied, a DC current will form solid-state plasma consisting of free carriers (electrons and holes) on the surface. The plasma has metal-like characteristics, that is, a reflection action for electromagnetic waves, and the reflection characteristic is closely related to microwave transmission characteristics, concentration and distribution of the surface plasma.

(12) In the following, a preparation method for a platform-shaped active region based P-I-N diode string in a reconfigurable loop antenna prepared by the disclosure will be further described in detail. In the drawings, for the purpose of convenient explanation, the thicknesses of layers and regions are zoomed in or out, and the shown sizes do not represent actual sizes.

(13) Referring to FIG. 2, and FIG. 2 is a flowchart of a preparation method for a platform-shaped active region based P-I-N diode string in a reconfigurable loop antenna according to an embodiment of the disclosure. The method is suitable for preparing an SOI-based transverse P-I-N diode, and the platform-shaped active region based P-I-N diode is mainly used for manufacturing the reconfigurable loop antenna. The method includes following steps of:

(14) (a) selecting an SOI substrate;

(15) in particular, for the step (a), the cause of adopting the SOI substrate is that a good microwave characteristic is required for the solid-state plasma antenna, while in order to meet this requirement, the P-I-N diode needs to possess good isolation characteristic and limiting capacity for carriers, i.e., the solid-state plasma; and SiO.sub.2 can limit the carriers, i.e., the solid-state plasma within a top silicon layer, and thus the SOI is preferably adopted as a substrate of the solid-state plasma P-I-N diode;

(16) (b) etching the SOI substrate to form a platform-shaped active region;

(17) (c) depositing a P-type Si (silicon) material and an N-type Si material around the platform-shaped active region by an in-situ doping process to form a P region and an N region respectively;

(18) (d) depositing a polysilicon (Poly-Si) material around the platform-shaped active region by a chemical vapor deposition (CVD) process;

(19) (e) depositing a fourth protective layer on an entire surface of the substrate by a CVD process;

(20) (f) activating impurities in the P region and N region by an annealing process; and

(21) (g) forming leads on a surface of the polysilicon material and forming PADs by photolithography, to form the P-I-N diode string.

(22) In an embodiment of the disclosure, the step (b) includes:

(23) (b1) forming a first protective layer on a surface of the SOI substrate by a CVD process;

(24) (b2) using a photolithography process with a first mask to form an active region pattern on the first protective layer; and

(25) (b3) etching the first protective layer and the top Si layer of the SOI substrate in designated positions around the active region pattern by a dry etching process.

(26) In an embodiment of the disclosure, after the step (b), the method further includes:

(27) (x1) oxidizing sidewalls of the platform-shaped active region by an oxidizing process to form an oxide layer on the sidewalls of the platform-shaped active region; and

(28) (x2) etching the oxide layer by a wet etching process to planarize the sidewalls of the platform shaped active region.

(29) The benefits of the steps (x1) and (x2) are to prevent protrusions on the sidewalls of trenches from forming an electric field concentrated region and prevent from causing breakdown of the P-i and N-i junctions.

(30) In an embodiment of the disclosure, the step (c) includes:

(31) (c1) depositing a second protective layer on an entire surface of the substrate;

(32) (c2) forming a P region pattern on a surface of the second protective layer by a photolithography process with a second mask;

(33) (c3) removing the second protective layer on the P region pattern by a wet etching process;

(34) (c4) depositing the P-type Si material on a sidewall of the platform-shaped active region to faun the P region by the in-situ doping process;

(35) (c5) depositing a third protective layer on an entire surface of the substrate;

(36) (c6) forming an N region pattern on a surface of the third protective layer by a photolithography process with a third mask;

(37) (c7) removing the third protective layer on the N region pattern by a wet etching process; and

(38) (c8) depositing the N-type Si material on another sidewall of the platform-shaped active region to form the N region by the in-situ doping process.

(39) It should be noted that in a conventional preparation process for the P region and the N region of the P-I-N diode, an implantation process is adopted for the formations of the P and N regions, but such conventional method requires larger implantation dosage and energy, has high requirements on equipment and is incompatible with the existing process. However, if a diffusion process is adopted, a junction depth is deeper, but the P region and N region have larger areas, resulting in a low integration level and an uneven doping concentration, thereby affecting electrical properties of the P-I-N diode and leading to poor controllability in concentration and distribution of the solid-state plasma.

(40) Adverse effects caused by the ion implantation manner can be avoided by adopting the in-situ doping, and the doping concentration of a material can be controlled by controlling a gas flow, and it is favorable for obtaining a steep doping interface, thereby obtaining better device performances.

(41) In an embodiment of the disclosure, the step (c4) includes:

(42) (c41) depositing the P-type Si material on the sidewall of the platform-shaped active region by the in-situ doping process;

(43) (c42) etching the P-type Si material by a dry etching process with a fourth mask to form the P region on the sidewall of the platform-shaped active region; and

(44) (c43) removing the second protective layer on an entire surface of the substrate by a selective etching process.

(45) In an embodiment of the disclosure, the step (c8) includes:

(46) (c81) depositing the N-type Si material the another sidewall of the platform-shaped active region by the in-situ doping process;

(47) (c82) etching the N-type Si material by a dry etching process with a fifth mask to form the N region on the another sidewall of the platform-shaped active region; and

(48) (c83) removing the third protective layer on an entire surface of the substrate by a selective etching process.

(49) In an embodiment of the disclosure, the step (g) includes:

(50) (g1) forming a lead hole pattern on a surface of the fourth protective layer by a photolithography process with a sixth mask;

(51) (g2) etching the fourth protective layer to expose a part of the polysilicon material by an anisotropic etching process to form the lead holes;

(52) (g3) sputtering a metal material into the lead holes to form a metal silicide; and

(53) (g4) performing a passivation treatment, forming PADs by photolithography and performing an interconnection, to thereby obtain the P-I-N diode string.

(54) The embodiment of the disclosure uses the in-situ doping process to prepare and provide the high-performance platform-shaped active region based P-I-N diode suitable for forming a solid-state plasma antenna.

(55) Referring to FIGS. 7A to 7S, FIGS. 7A to 7S are schematic views of another preparation method for a platform-shaped active region based P-I-N diode in a reconfigurable loop antenna according to an embodiment of the disclosure. Based on the above embodiment, the preparation of a platform-shaped active region based P-I-N diode that a length of a solid-state plasma region is 100 micrometers is taken as an example for explanation in detail. The specific steps are as follows.

(56) S10: an SOI substrate is selected.

(57) Referring to FIG. 7A, a crystal orientation of the SOI substrate is (100), the SOI substrate 101 has a doping type of P-type and a doping concentration of 10.sup.14 cm.sup.3, and a thickness of a top Si layer for example is 20 m.

(58) S20: a layer of silicon nitride (SiN) is deposited on a surface of the SOI substrate.

(59) Referring to FIG. 7B, a chemical vapor deposition (CVD) method is adopted to deposit a SiN layer 201 on the SOI substrate 101.

(60) S30: the SOI substrate is etched to form trenches for an active region.

(61) Referring to FIG. 7C-1, a platform-shaped active region pattern is formed on the SiN layer by a photolithography process, the protective layer and the top Si layer are etched in designated positions of the active region pattern by a dry etching process to form a platform-shaped active region 301, and a top view refers to FIG. 7C-2.

(62) S40: the periphery of the platform is flattened/planarized.

(63) Referring to FIG. 7D-1 the peripheral sidewalls of the platform active region is oxidized to make the peripheral sidewalls of the platform active region be formed with an oxide layer 401, and a top view refers to FIG. 7D-2.

(64) Referring to FIG. 7E-1, the oxide layer on the peripheral sidewalls of the platform active region is etched off by a wet etching process to planarize the peripheral sidewalls of the platform active region, and a top view refers to FIG. 7E-2.

(65) S50: a layer of silicon oxide (SiO.sub.2) is deposited on a surface of the substrate.

(66) Referring to FIG. 7F, a layer of SO.sub.2 601 is deposited on the substrate by a CVD method.

(67) S60: the SiO.sub.2 layer is patterned by photolithography.

(68) Referring to FIG. 7G, a P region pattern is formed on the SiO.sub.2 layer by a photolithography process, and the SiO.sub.2 layer on the P region pattern is removed by a wet etching process.

(69) S70: a P region is formed.

(70) Referring to FIG. 7H, a specific method includes depositing a P-type Si on the P region pattern on a surface of the SOI substrate to form a P region 801, and a doping concentration of the P region is controlled by controlling a gas flow.

(71) S80: the surface of the substrate is planarized.

(72) Referring to FIG. 7I, a specific method includes planarizing a surface of the P region by a dry etching process, and then removing the SiO.sub.2 layer on the surface of the substrate by a wet etching process.

(73) S90: a layer of SiO.sub.2 is deposited on the surface of the substrate.

(74) Referring to FIG. 7J, a SiO.sub.2 layer is deposited on the surface of the substrate by a CVD method.

(75) S100: the SiO.sub.2 layer is patterned by photolithography.

(76) Referring to FIG. 7K, N region pattern is formed on the SiO.sub.2 layer by a photolithography process, and the SiO.sub.2 layer on the N region is removed by a wet etching process.

(77) S110: an N region is formed.

(78) Referring to FIG. 7L, an N-type Si is deposited on an N region pattern on the surface of the SOI substrate by an in-situ doping method to form an N region 1201, and a doping concentration of the N region is controlled by controlling a gas flow.

(79) S120: the surface of the substrate is planarized.

(80) Referring to FIG. 7M, a surface of the N region is planarized by a dry etching process, and then the SiO.sub.2 layer on the surface of the substrate is removed by a wet etching process.

(81) S130: a polysilicon layer is deposited.

(82) Referring to FIG. 7N, a polysilicon layer 1401 is sputtered into the trenches by a CVD method.

(83) S140: a SiO.sub.2 layer is formed on the surface.

(84) Referring to FIG. 7O a SiO.sub.2 layer 1501 with a thickness of 500 nm is deposited on the surface by a CVD method.

(85) S150: the surface is flattened/planarized.

(86) Referring to FIG. 7P, the SiO.sub.2 and SiN layers on the surface are removed by adopting a chemical mechanical polishing (CMP) method, such that the surface is flattened.

(87) S160: impurities are activated.

(88) At 950-1150 degrees Celsius, ion implanted impurities are activated by annealing for 0.5-2 min, and the impurities in the active region are propelled.

(89) S170: lead holes are formed by photolithography.

(90) Referring to FIG. 7Q, the lead holes 1701 are formed by photolithography in the SiO.sub.2 layer.

(91) S180: leads are formed.

(92) Referring to FIG. 7R, a metal is sputtered into the surface of the substrate and then is alloyed to form a metal silicide, and the metal on the surface is etched; then a metal 1801 is sputtered onto the surface of the substrate and the leads are formed by photolithography.

(93) S190: a passivation treatment is performed and PADs are formed by photolithography.

(94) Referring to FIG. 7S, a passivation layer 1901 can be formed by depositing SiN and PADs are formed by photolithography. Consequently, the P-I-N diode is formed as a material for preparing the solid-state plasma antenna.

(95) Referring to FIG. 8, FIG. 8 is a structural schematic view of another platform-shaped active region based P-I-N diode in a reconfigurable loop antenna according to an embodiment of the disclosure. The P-I-N diode is prepared by the preparation method as shown in FIG. 2. Specifically, the P-I-N diode is prepared on an SOI substrate 301, and a P region 304 and an N region 305 of the P-I-N diode and an I region (i.e., intrinsic region) transversely located between the P region 304 and the N region 305 are all located in top Si layer 302 of the SOI substrate.

(96) In summary, specific examples are used herein to describe the principle and implementation manners of the P-I-N diode and its preparation method of the disclosure, and the description of the foregoing embodiments is merely used to help understand the method and core idea of the disclosure. At the same time, for those skilled in the art, according to the idea of the disclosure, some changes may be made in the specific implementations and application ranges. Sum up, the content of the present specification should not be construed as a limitation of disclosure. The protection scope of the disclosure should be covered by the appended claims.

INDUSTRIAL APPLICABILITY

(97) Adverse effects caused by the ion implantation manner can be avoided by adopting the in-situ doping in the embodiments of the disclosure, and the doping concentration of a material can be controlled by controlling a gas flow, and it is favorable for obtaining a steep doping interface, thereby obtaining better device performances. The P-I-N diode plasma reconfigurable antenna may be composed of SOI based PIN diodes arranged in an array, by use of selective conductions of the P-I-N diodes in the array through an external control, the array would form dynamic solid-state plasma stripes and thus achieve the function of antenna and have transmitting and receiving functions for specific electromagnetic waves. Moreover, the antenna can change the solid-state plasma stripes in shape and distribution by use of selective conductions of the P-I-N diodes in the array and thereby realize the reconstruction of antenna, so that has important application prospects in the defense communications and radar technologies.