A sintering powder comprising: a first type of metal particles having a mean longest dimension of from 100 nm to 50 μm.

A method for forming a connection between two connection partners includes: forming a pre-connection layer on a first surface of a first connection partner, the pre-connection layer including a certain amount of liquid; performing a pre-connection process, thereby removing liquid from the pre-connection layer; performing photometric measurements while performing the pre-connection process, wherein performing the photometric measurements includes determining at least one photometric parameter of the pre-connection layer, wherein the at least one photometric parameter changes depending on the fluid content of the pre-connection layer; and constantly evaluating the at least one photometric parameter, wherein the pre-connection process is terminated when the at least one photometric parameter is detected to be within a desired range.

A method for forming a connection between two connection partners includes: forming a pre-connection layer on a first surface of a first connection partner, the pre-connection layer including a certain amount of liquid; performing a pre-connection process, thereby removing liquid from the pre-connection layer; performing photometric measurements while performing the pre-connection process, wherein performing the photometric measurements includes determining at least one photometric parameter of the pre-connection layer, wherein the at least one photometric parameter changes depending on the fluid content of the pre-connection layer; and constantly evaluating the at least one photometric parameter, wherein the pre-connection process is terminated when the at least one photometric parameter is detected to be within a desired range.

A power inverter module includes a base module having a plurality of electrically conductive layers, including a first conductive layer, a second conductive layer and a third conductive layer. A first terminal is operatively connected to the first conductive layer at a first end and a second terminal is operatively connected to the second conductive layer at the first end. An isolation sheet is sandwiched between the first and second terminals. The first terminal and the second terminal include a respective proximal portion composed of a first material and a respective distal portion composed of a second material. At least one of the first terminal and the second terminal is bent to create an overlap zone such that a gap between the first terminal and the second terminal in the overlap zone is less than a threshold distance. The power inverter module is configured to reduce parasitic inductance.

A power inverter module includes a base module having a plurality of electrically conductive layers, including a first conductive layer, a second conductive layer and a third conductive layer. A first terminal is operatively connected to the first conductive layer at a first end and a second terminal is operatively connected to the second conductive layer at the first end. An isolation sheet is sandwiched between the first and second terminals. The first terminal and the second terminal include a respective proximal portion composed of a first material and a respective distal portion composed of a second material. At least one of the first terminal and the second terminal is bent to create an overlap zone such that a gap between the first terminal and the second terminal in the overlap zone is less than a threshold distance. The power inverter module is configured to reduce parasitic inductance.

A method of manufacturing a semiconductor device includes: applying a bonding resin composition on a semiconductor chip supporting member, the bonding resin composition containing a thermosetting resin and silver microparticles having an average particle size of 10 to 200 nm, the silver microparticles having a protective layer made of an organic compound on surfaces thereof; a semi-sintering step of heating the applied bonding resin composition at a temperature that is lower than a reaction starting temperature of the thermosetting resin and is equal to or more than 50 C. to bring the silver microparticles into a semi-sintered state; and a bonding step including: placing a semiconductor chip on the bonding resin composition containing the silver microparticles in a semi-sintered state, heating at a temperature higher than the reaction starting temperature of the thermosetting resin in a pressure-free state, and bonding the semiconductor chip to the semiconductor chip supporting member.

A sintered member is provided between a semiconductor chip and a terminal. The sintered member is made of a sinter sheet by heating and pressing the same. The semiconductor chip is connected to the terminal via the sintered member. Convex portions are formed at a front-side surface of the semiconductor chip. Concave portions, each of which has such a shape corresponding to that of each convex portion of the semiconductor chip, are formed at a surface of the sintered member facing to the semiconductor chip.

A device (2) is formed on a main surface of a substrate (1). The main surface of the substrate (1) is bonded to the undersurface of the counter substrate (14) via the bonding member (11,12,13) in a hollow state. A circuit (17) and a bump structure (26) are formed on the top surface of the counter substrate (14). The bump structure (26) is positioned in a region corresponding to at least the bonding member (11,12,13), and has a higher height than that of the circuit (17).

A wafer-level packaging method and a package structure are provided. In the method, a first wafer is provided having first chips formed there-in. A surface of each first chip is integrated with a first electrode. A first dielectric layer is formed on the first wafer to expose each first electrode. Second chips are provided with a surface of each second chip integrated with a second electrode. A second dielectric layer is formed on the plurality of second chips to expose each second electrode. The second dielectric layer is positioned relative to the first dielectric layer. The second chips are bonded to the first wafer with each second chip aligned relative to one first chip to form a cavity there-between. A chip interconnection structure is formed in the cavity to electrically connect the first electrode with the second electrode. An encapsulation layer covers the second chips.

A semiconductor device includes an insulative substrate, a wiring pattern, a bonding portion, and a semiconductor element. The wiring pattern is formed on an upper surface of the insulative substrate. The bonding portion is formed on an upper surface of the wiring pattern. The semiconductor element includes an electrode pad connected to an upper surface of the bonding portion. The bonding portion includes first sintered layers distributed in the bonding portion and a second sintered layer having a density differing from each of the first sintered layers and surrounding the first sintered layer.