A semiconductor element bonding structure capable of strongly bonding a semiconductor element and an object to be bonded and relaxing thermal stress caused by a difference in thermal expansion, by interposing metal particles and Ni between the semiconductor element and the object to be bonded, the metal particles having a lower hardness than Ni and having a micro-sized particle diameter. A plurality of metal particles 5 (aluminum (Al), for example) having a lower hardness than nickel (Ni) and having a micro-sized particle diameter are interposed between a semiconductor chip 3 and a substrate 2 to be bonded to the semiconductor chip 3, and the metal particles 5 are fixedly bonded by the nickel (Ni). Optionally, aluminum (Al) or an aluminum alloy (Al alloy) is used as the metal particles 5, and aluminum (Al) or an aluminum alloy (Al alloy) is used on the surface of the semiconductor chip 3 and/or the surface of the substrate 2.

An electronic device comprises a semiconductor die, a layer stack disposed on the semiconductor die and comprising one or more functional layers, wherein the layer stack comprises a protection layer which is an outermost functional layer of the layer stack, and a sacrificial layer disposed on the protection layer, wherein the sacrificial layer comprises a material which decomposes or becomes volatile at a temperature between 100° and 400° C.

In a method for connecting components during production of power electronics modules or assemblies, surfaces of the components have a metallic surface layer upon supply, or are furnished therewith, wherein the layer has a surface that is smooth enough to allow direct bonding or is smoothed to obtain a surface that is smooth enough to allow direct bonding. The surface layers of the surfaces that are to be connected are then pressed against each other with a pressure of at least 5 MPa at elevated temperature, so that they are joined to each other, forming a single layer. The method enables simple, rapid connection of even relatively large contact surfaces, which satisfies the high requirements of power electronics modules.

A method utilized at a sintered metal layer bonding a semiconductor element and a support substrate together suppresses cracks appearing in the sintered metal layer, and damage to the semiconductor element. A semiconductor device includes a support substrate, a semiconductor element, and a sintered metal layer bonding the support substrate and the semiconductor element. The sintered metal layer has a low porosity region disposed inward of an outer edge of the semiconductor element with the sintered metal layer bonded to the semiconductor element. The region is lower in porosity than the remaining sintered metal layer, and is formed as a wall-shaped structural body having an elongated string and extending from an upper surface to a lower surface of the sintered metal layer. The low porosity region is disposed to surround a region immediately below a center of the semiconductor element along the outer edge of the semiconductor element.

A manufacturing method includes the step of laminating a sheet assembly onto chips arranged on a processing tape, where the sheet assembly has a multilayer structure including a base and a sinter-bonding sheet and is laminated so that the sinter-bonding sheet faces the chips, and subsequently removing the base B from the sinter-bonding sheet. The chips on the processing tape are picked up each with a portion of the sinter-bonding sheet adhering to the chip, to give sinter-bonding material layer-associated chips. The sinter-bonding material layer-associated chips are temporarily secured through the sinter-bonding material layer to a substrate. The sinter-bonding material layers lying between the temporarily secured chips and the substrate are converted through a heating process into sintered layers, to bond the chips to the substrate. The semiconductor device manufacturing method is suitable for efficiently supplying a sinter-bonding material to semiconductor chips while reducing loses of the sinter-bonding material.

A power semiconductor element and a support member are stacked with an intermediate structure being interposed between the power semiconductor element and the support member. The intermediate structure includes a first metal paste layer and at least one first penetrating member. The first metal paste layer contains a plurality of first metal particles. The at least one first penetrating member penetrates the first metal paste layer. At least one first vibrator attached to the at least one first penetrating member penetrating the first metal paste layer is vibrated. The first metal paste layer is heated so that the plurality of first metal particles are sintered or fused.

Semiconductor dies including ultra-thin wafer backmetal systems, microelectronic devices containing such semiconductor dies, and associated fabrication methods are disclosed. In one embodiment, a method for processing a device wafer includes obtaining a device wafer having a wafer frontside and a wafer backside opposite the wafer frontside. A wafer-level gold-based ohmic bond layer, which has a first average grain size and which is predominately composed of gold, by weight, is sputter deposited onto the wafer backside. An electroplating process is utilized to deposit a wafer-level silicon ingress-resistant plated layer over the wafer-level Au-based ohmic bond layer, while imparting the plated layer with a second average grain size exceeding the first average grain size. The device wafer is singulated to separate the device wafer into a plurality of semiconductor die each having a die frontside, an Au-based ohmic bond layer, and a silicon ingress-resistant plated layer.

A method for producing a stable sandwich arrangement of two components with solder situated therebetween, comprising the steps:

(1) providing two components, each having at least one contact surface, and a free solder preform,
(2) producing a sandwich arrangement of the components and a solder preform arranged between them and thus not yet connected to them by bringing into contact (i) each one of the contact surfaces, (ii) each of the single contact surface of the components or (iii) one of the contact surfaces of one component and a single contact surface of the other component, with the contact surfaces of the free solder preform, and
(3) hot-pressing the sandwich arrangement produced in step (2) so as to form the stable sandwich arrangement at a temperature being at 10 to 40% below the melting temperature of the solder metal of the solder preform, expressed in ° C.

A method for producing a component bonded to a solder preform, comprising the following steps: (1) providing a component having at least one contact surface, and a free solder preform, (2) producing an assembly of the component and the solder preform, which is not yet bonded to said component, by bringing a contact surface, or the sole contact surface, of the component into contact with a contact surface of the free solder preform, and (3) forming the component bonded to the solder preform by hot pressing the assembly produced in step (2) at a temperature that is 10 to 40% lower than the melting temperature of the soldering metal of the solder preform, expressed in ° C., and with a combination of pressing force and pressing duration that will effect a reduction of 10% in the original thickness of the originally free solder preform.

Disclosed is a method of bonding two copper structures involving compressing a first copper structure with a second copper structure under a stress from 0.1 MPa to 50 MPa and under a temperature of 250 C. or less so that a bonding surface of the first copper structure is bonded to a bonding surface of the second copper structure; at least one of the bonding surface of the first copper structure and the bonding surface of the second copper structure have a layer of nanograins of copper having an average grain size of 5 nm to 500 nm, the layer of the nanograins of copper having a thickness of 10 nm to 10 m.