Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing.

An acoustic wave device includes: a first substrate; a first acoustic wave filter located on a first surface of the first substrate; a pad that is located on the first surface and electrically separated from the first acoustic wave filter in the first surface; a ground pattern that is located on the first surface, and is located between the pad and the first acoustic wave filter in the first surface; and a second acoustic wave filter that is electrically connected to the pad, and at least partially overlaps with the first acoustic wave filter in plan view.

An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines in direct contact with a top surface of one or more devices and one or more vias in direct contact with top surfaces of the one or more metal lines. The interconnect structure also includes one or more dielectric pillars in direct contact with the top surface of the one or more devices. A height of a top surface of the one or more dielectric pillars above the one or more devices is equal to a height of a top surface of the one or more vias above the one or more devices.

The present disclosure relates to a microelectromechanical systems (MEMS) package featuring a flat plate having a raised edge around its perimeter serving as an anti-stiction device, and an associated method of formation. A CMOS IC is provided having a dielectric structure surrounding a plurality of conductive interconnect layers disposed over a CMOS substrate. A MEMS IC is bonded to the dielectric structure such that it forms a cavity with a lowered central portion the dielectric structure, and the MEMS IC includes a movable mass that is arranged within the cavity. The CMOS IC includes an anti-stiction plate disposed under the movable mass. The anti-stiction plate is made of a conductive material and has a raised edge surrounding at least a part of a perimeter of a substantially planar upper surface.

In examples, an electronic device comprises a printed circuit board (PCB), an orifice extending through the PCB, and a semiconductor die suspended above the orifice by aluminum bond wires. The semiconductor die is vertically aligned with the orifice and the bond wires coupled to the PCB.

Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device comprises a substrate, a stack structure on the substrate, and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions. The stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions.

An integrated circuit includes an interconnect which includes a metal layer, a layer of graphene on at least one of the top surface of the interconnect or the bottom surface of the interconnect, and a layer of hexagonal boron nitride (hBN) on the layer of graphene, opposite from the metal layer. Dielectric material of the integrated circuit contacts the layer of hBN. The layer of graphene has one or more atomic layers of graphene. The layer of hBN is one to three atomic layers thick. The interconnect may have a lower graphene layer on the bottom surface of the metal layer with a lower hBN layer, and an upper graphene layer on the top surface of the metal layer, with an upper hBN layer.

A method for forming trenches of an interconnect network in a substrate. The method includes forming a first trench in the substrate, which has a first width. The method also includes forming a second trench in the substrate, which has a second width that is greater than the first width. The method also includes depositing a metal layer into the trenches, applying a dielectric over the metal, and diffusing metal atoms from the trenches to the dielectric. The dielectric absorbs a majority of the metal atoms from the first trench while simultaneously absorbing only a minority of metal atoms from the second trench.

A method is provided for fabricating a semiconductor structure. The method includes providing a substrate having a dielectric layer formed on the substrate, where an opening is formed in the dielectric layer, and bottom of the opening exposes surface of the substrate. The method also includes forming a first metal layer over of the dielectric layer, where a temperature for forming the first metal layer is a first temperature. In addition, the method includes forming a second metal layer filling the opening, where a temperature for forming the second metal layer is a second temperature, and the second temperature is higher than the first temperature. Further, the method includes planarizing the second metal layer and the first metal layer until the top surface of the dielectric layer is exposed.

An acoustic wave device includes: a first piezoelectric substrate; a first IDT that includes a plurality of first electrode fingers and is located on a first surface of the first piezoelectric substrate; a second piezoelectric substrate that is located above the first surface; and a second IDT that is located on a second surface of the second piezoelectric substrate, and includes a plurality of second electrode fingers that are non-parallel to the plurality of first electrode fingers, the second surface of the second piezoelectric substrate facing the first surface across an air gap.