A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

A method for forming trenches of an interconnect network in a substrate. The method includes forming a first trench in the substrate, which has a first width. The method also includes forming a second trench in the substrate, which has a second width that is greater than the first width. The method also includes depositing a metal layer into the trenches, applying a dielectric over the metal, and diffusing metal atoms from the trenches to the dielectric. The dielectric absorbs a majority of the metal atoms from the first trench while simultaneously absorbing only a minority of metal atoms from the second trench.

An acoustic wave device includes: a first piezoelectric substrate; a first IDT that includes a plurality of first electrode fingers and is located on a first surface of the first piezoelectric substrate; a second piezoelectric substrate that is located above the first surface; and a second IDT that is located on a second surface of the second piezoelectric substrate, and includes a plurality of second electrode fingers that are non-parallel to the plurality of first electrode fingers, the second surface of the second piezoelectric substrate facing the first surface across an air gap.

The present disclosure provides an interconnect structure, including a substrate having a conductive region adjacent to a gate region, a contact over the conductive region, a first interlayer dielectric layer (ILD) surrounding the contact, a via over the contact, a first densified dielectric layer surrounding the via, wherein the densified dielectric layer has a first density, and a second ILD layer over the first ILD layer and surrounding the via, wherein the second ILD layer has a second density, the first density is greater than a second density.

A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.

Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.

Disclosed herein is an interconnect structure, including: a dielectric material layer having a cavity having a height, width and length within a dielectric material layer wherein the width is less than or equal to about 100 nanometers and the height to width ratio is less than or equal to about 2.5; a diffusion barrier liner layer disposed in the cavity on the dielectric material; an optional crystallization seed layer disposed on the diffusion barrier liner layer; and a conductive material disposed on the crystallization seed layer when present and filling the opening. When the crystallization seed layer is not present the conductive material is disposed on the diffusion barrier liner.

A method of manufacturing a semiconductor device includes providing a first semiconductor chip comprising a first metallic structure, a first surface and a second surface opposite to the first surface; providing a second semiconductor chip comprising a second metallic structure; bonding the first semiconductor chip with the second semiconductor chip on the second surface; forming a first recessed portion including a first sidewall and a first bottom surface coplanar with a top surface of the first metallic structure; forming a second recessed portion including a second sidewall and a second bottom surface coplanar with a top surface of the second metallic structure; forming a dielectric layer over the first sidewall and the second sidewall; and forming a conductive material over the dielectric layer, the top surface of the first metallic structure and the top surface of the second metallic structure.

An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.