A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate, a first resistive element and a second resistive element over the semiconductor substrate. A topmost surface of the second resistive element is higher than a topmost surface of the first resistive element. The semiconductor device structure also includes a first conductive feature and a second conductive feature electrically connected to the first resistive element. The second resistive element is between and electrically isolated from the first conductive feature and the second conductive feature. The semiconductor device structure further includes a first dielectric layer surrounding the first conductive feature and the second conductive feature.

One illustrative device disclosed herein includes a semiconductor substrate and a bipolar junction transistor (BJT) device that comprises a collector region, a base region and an emitter region. In this example, the device also includes a field effect transistor and at least one base conductive contact structure that conductively and physically contacts the base region.

A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

There are provided a transistor including a first semiconductor layer of a first conductivity type, a second semiconductor layer thereabove, a first impurity region of a second conductivity type provided in an upper layer part of the second semiconductor layer, a second impurity region of a first conductivity type provided in an upper layer part of the first impurity region, a gate electrode facing the first impurity region and the second semiconductor layer with a gate insulating film interposed in between, and first and second main electrodes; a parasitic transistor with the second impurity region as a collector, the first and the second semiconductor layers as an emitter, and the first impurity region as a base; a parasitic diode with the first impurity region as an anode, and the first and the second semiconductor layers as a cathode; and a pn junction diode with the first impurity region as an anode, and the second impurity region as a cathode.

A first silicon oxide film is formed on the inner wall of a deep trench by oxidizing the inner wall of the deep trench while heating the inner wall. Then, a second silicon oxide film is formed using at least one of atmospheric pressure CVD and plasma CVD so that the second silicon oxide film covers the first silicon oxide film in the deep trench.

A host electronic device may be coupled to an accessory electronic device. The host device and the accessory device may be connected via power supply lines and user data lines. If the host and accessory devices are improperly connected or if the accessory device is exposed to an incorrect voltage environment, the internal circuitry on the accessory device can be damaged. The accessory device may therefore include a reverse voltage protection circuit that can help prevent a large amount of current from inadvertently flowing into the accessory device. The protection circuit may include a low-side-enabled reverse current protection switch coupled between the external and internal ground terminals and also a single low-drop switch coupled to each of the user data lines. The low-drop switch will be activated whenever the voltage at the external ground terminal exceeds the voltage at the data line to help deactivate low-side-enabled reverse current protection switch.

A semiconductor device includes: a drift layer; a base layer on the drift layer; a collector layer and a cathode layer opposite to the base layer; multiple trenches penetrating the base layer; a gate electrode in each trench; an emitter region in a surface portion of the base layer and contacting each trench; a first electrode connected to the base layer and the emitter region; and a second electrode connected to the collector layer and the cathode layer. The gate electrodes in a diode region of a semiconductor substrate are controlled independently from the gate electrodes in the IGBT region. A voltage not forming an inversion layer in the base layer is applied to the gate electrodes in the diode region.

This electrostatic protection circuit enables a high hold voltage to be set, and acts to accurately prevent breakdown of a protected circuit immediately after power on, and to prevent breakdown or deterioration of a protection device during prolonged normal operation, without connecting a resistance element in parallel to a plurality of circuit blocks connected in series. This electrostatic protection circuit is provided with a plurality of circuit blocks connected in series between a first node and a second node, at least one circuit block out of the plurality of circuit blocks including a thyristor having an anode connected to one end of the at least one circuit block and a cathode connected to the other end of the at least one circuit block. When the potential of the first node is higher than the potential of the second node during normal operation, the voltage between both ends of the other circuit blocks out of the plurality of circuit blocks is smaller than the voltage between the anode and the cathode of the thyristor.

One illustrative method disclosed includes forming an isolation structure so as to define first and second active regions on the SOI substrate, forming a field effect transistor above the first active region and forming an opening in the second active region that exposes an upper surface of the bulk semiconductor layer in the second active region. In this example, the method further includes performing a common epitaxial growth process so as to form an epi semiconductor material region above each of the source/drain regions of the transistor and to form a unitary epi semiconductor structure above the second active region, wherein the unitary epi semiconductor structure is formed on and in contact with the exposed upper surface of the bulk semiconductor layer within the opening and on and in contact with an upper surface of the active layer in the second active region.

A semiconductor device that allows easy hole extraction is provided. The semiconductor device includes: a semiconductor substrate having drift and base regions; a transistor portion formed in the semiconductor substrate; and a diode portion formed adjacent to the transistor portion and in the semiconductor substrate. In the transistor portion and the diode portion: a plurality of trench portions each arrayed along a predetermined array direction; and a plurality of mesa portions formed between respective trench portions are formed, among the plurality of mesa portions, at least one boundary mesa portion at a boundary between the transistor portion and the diode portion includes a contact region at an upper surface of the semiconductor substrate and having a concentration higher than that of the base region, and an area of the contact region at the boundary mesa portion is greater than an area of the contact region at another mesa portion.