An embodiment of a semiconductor device includes a plurality of transistor sections separated from each other and a plurality of diode sections separated from each other. Each transistor section includes an emitter electrode and a collector electrode. Each diode section includes an anode electrode and a cathode electrode. Each transistor section is electrically coupled to a common gate pad. A ratio between an active transistor part and an active diode part of the semiconductor device is adjustable by activating a first number of the transistor sections by selectively contacting the emitter electrodes and the collector electrodes of the first number of transistor sections, and by activating a second number of the diode sections by selectively contacting the anode electrodes and the cathode electrodes of the second number of diode sections.

A semiconductor device includes a sub-collector layer disposed on a substrate, a bipolar transistor including a collector layer formed of a semiconductor having a lower carrier concentration than the sub-collector layer, a base layer, and an emitter layer, and a protection diode including a Schottky electrode. The Schottky electrode forms, in a partial region of an upper surface of the collector layer, a Schottky junction to the collector layer and is connected to one of the base layer and the emitter layer. In the collector layer, a part that forms a junction to the base layer and a part that forms a junction to the Schottky electrode are electrically connected to each other via the collector layer.

A semiconductor device includes a semiconductor substrate, a transistor, and a first harmonic termination circuit. The transistor is formed at the semiconductor substrate. The transistor amplifies an input signal supplied to an input end and outputs an amplified signal through an output end. The first harmonic termination circuit attenuates a harmonic component included in the amplified signal. The first harmonic termination circuit is formed at the semiconductor substrate such that one end of the first harmonic termination circuit is connected to the output end of the transistor and the other end of the first harmonic termination circuit is connected to a ground end of the transistor.

A power amplifier apparatus includes a semiconductor substrate, a plurality of first transistors on the semiconductor substrate, a plurality of second transistors, at least one collector terminal electrically connected to collectors of the plurality of first transistors, a first inductor having a first end electrically connected to the collector terminal and a second end electrically connected to a power supply potential, at least one emitter terminal electrically connected to emitters of the plurality of second transistors and adjacent to the collector terminal in a second direction, a second inductor having a first end electrically connected to the emitter terminal and a second end electrically connected to a reference potential, and at least one capacitor having a first end electrically connected to the collectors of the plurality of first transistors and a second end electrically connected to the emitters of the plurality of second transistors.

An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.

An electronic device can include a substrate defining a trench. In an embodiment, a semiconductor body can be within the trench, wherein the semiconductor body has a resistivity of at least 0.05 ohm-cm and is electrically isolated from the substrate. In an embodiment, an electronic component can be within the semiconductor body. The electronic component can be a resistor or a diode. In a particular embodiment, the semiconductor body has an upper surface, the electronic component is within and along an upper surface and spaced apart from a bottom of the semiconductor body. In a further embodiment, the electronic device can further include a first electronic component within an active region of the substrate, an isolation structure within the trench, and a second electronic component within the isolation structure.

An integrated electronic device forming a power device and including: a semiconductor body; a first conductive region and a second conductive region, which extend over the semiconductor body, the second conductive region surrounding the first conductive region at a distance; and an edge termination structure, which is arranged between the first and second conductive regions and includes a dielectric region, which delimits an active area of the power device, and a semiconductive structure, which extends over the dielectric region and includes a plurality of diode chains, each diode chain including a plurality of first semiconductive regions of a first conductivity type and a plurality of second semiconductive regions of a second conductivity type, the first and second semiconductive regions being arranged in alternating fashion so as to form a series circuit including a plurality of first and second diodes, which are spaced apart from one another and have opposite orientations.

A semiconductor device includes a semiconductor substrate having a first region and a second region. The semiconductor device also includes an insulating structure laterally between the first region and the second region in the semiconductor substrate. The insulating structure electrically insulates the first region laterally from the second region in the semiconductor substrate. The semiconductor device further includes a connecting structure at a surface of the semiconductor substrate. The connecting structure contacts at least a sub-structure of the insulating structure and at least one of the first region and the second region. At least a sub-structure of the connecting structure has an electrical resistivity greater than 1*10.sup.3 m and less than 1*10.sup.12 m.

A communication interface protection device includes a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal. Each of the first and second EOS protection switches includes a first semiconductor-controlled rectifier (SCR) and a second SCR and a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR. The first EOS protection device is configured to be activated in response to an EOS condition that causes a first bias between the first and second terminals, and wherein the second EOS protection device is configured to be activated in response to an EOS condition that causes a second bias between the first and second terminals.