A lateral superjunction includes a substrate layer, a selective epitaxy layer deposited on the substrate layer, a trench formed into the selective epitaxy layer to expose a portion of the substrate layer, a first layer of semiconductor deposited in the trench, a second layer of semiconductor deposited adjacent to the first layer, and a first end layer of semiconductor deposited adjacent to the first layer of semiconductor and a second end layer of semiconductor deposited adjacent to the second layer of semiconductor.

A nitride semiconductor device is provide, the nitride semiconductor device including: an epitaxial layer; and an ion implantation layer that is provided on the epitaxial layer over a continuous depth range that extends over 100 nm or longer, and has a P type doping concentration equal to or higher than 110.sup.17 cm.sup.3, wherein the ion implantation layer has a region with a crystal defect density equal to or lower than 110.sup.16 cm.sup.3, the region being located in a range which is on an upper-surface-side of an interface between the epitaxial layer and the ion implantation layer, and is within 100 nm from the interface.

A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

Diodes employing one or more Group III-Nitride polarization junctions. A III-N polarization junction may include two III-N material layers having opposite crystal polarities. The opposing polarities may induce a two-dimensional charge sheet (e.g., 2D electron gas) within each of the two III-N material layers. Opposing crystal polarities may be induced through introduction of an intervening layer between two III-N material layers. The intervening layer may be of a material other than a Group III-Nitride. Where a P-i-N diode structure includes two Group III-Nitride polarization junctions, opposing crystal polarities at a first of such junctions may induce a 2D electron gas (2DEG), while opposing crystal polarities at a second of such junctions may induce a 2D hole gas (2DHG). Diode terminals may then couple to each of the 2DEG and 2DHG.

The present invention relates to various high quality n-type and p-type doped gallium-based semiconductor materials, electronic components incorporating these materials, and processes of producing these materials. In particular, The present invention relates processes to achieve high quality, uniform doping of a whole wafer or a thin layer of gallium-based semiconductor materials for various applications such as a vertical power transistor or diode.

A method for mapping and analyzing a GaN substrate to identify areas of the substrate suitable for fabrication of electronic devices thereon. Raman spectroscopy is performed over the surface of a GaN substrate to produce maps of the E.sub.2 and A.sub.1 peaks at a plurality of areas on the substrate surface, the E.sub.2 and A.sub.1 peaks being associated with known concentrations of defects and charge carriers, so that areas of the GaN substrate having relatively high resistivity or conductivity which make those areas suitable or unsuitable for fabrication of electronic devices can be identified. The devices can then be fabricated only on suitable areas of the substrate, or the size of the devices can be tailored to maximize the yield of devices fabricated thereon. Substrates not meeting a threshold level of defect and/or charge carrier concentration can be discarded without fabrication of poor-quality devices thereon.

A semiconductor device, including an insulator formed on a top surface of a semiconductor substrate, a semiconductor layer, containing a first region of a first conductivity type, formed on the insulator layer, wherein the first region is a P+ region or an N+ region, a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region, wherein the P-N junction comprises a first portion parallel to the top surface of the semiconductor substrate, and the second region is the semiconductor substrate and partially covered by the semiconductor layer, a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region.

A method of fabricating an electronic device includes providing a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15 and 0.65. The method also includes growing a first III-V epitaxial layer coupled to the III-V substrate and growing a second III-V epitaxial layer coupled to the first III-V epitaxial layer. The method further includes forming a first contact in electrical contact with the III-V substrate and forming a second contact in electrical contact with the second III-V epitaxial layer.

A stacked III-V semiconductor diode having an n.sup. layer having a first surface, a second surface, a dopant concentration of 10.sup.12 N/cm.sup.3 to 10.sup.17 N/cm.sup.3 and a layer thickness of 50 m to 1,000 m, a p.sup.+ layer, which is integrally connected to the first surface and has a dopant concentration of 5.Math.10.sup.18 N/cm.sup.3 to 5.Math.10.sup.20 N/cm.sup.3, an n.sup.+ layer, which is integrally connected to the second surface and has a dopant concentration of at least 10.sup.19 N/cm.sup.3. The p.sup.+ layer, the n.sup. layer and the n.sup.+ layer each having a monolithic design and each being made up of a GaAs compound. The dopant concentration of the n.sup. layer having a first value on the first surface and a second value on the second surface, and the second value of the dopant concentration being greater than the first value at least by a factor between 1.5 and 2.5.

A stacked III-V semiconductor component having a p.sup.+ region with a top side, a bottom side, and a dopant concentration of 5.Math.10.sup.18-5.Math.10.sup.20 N/cm.sup.3, a first n.sup. layer with a top side and a bottom side, a dopant concentration of 10.sup.12-10.sup.17 N/cm.sup.3, and a layer thickness of 10-300 m, an n.sup.+ region with a top side, a bottom side, and a dopant concentration of at least 10.sup.18 N/cm.sup.3, wherein the p.sup.+ regions, the n.sup. layer, and the n.sup.+ region follow one another in the stated order, are each formed monolithically, and each comprise a GaAs compound or consist of a GaAs compound, the n.sup.+ region or the p.sup.+ region is formed as the substrate layer, and the n.sup. layer comprises chromium with a concentration of at least 10.sup.14 N/cm.sup.3 or at least 10.sup.15 N/cm.sup.3.