A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.

A method for manufacturing a semiconductor device of the present disclosure includes: ion-implanting impurities into a source-drain electrodes forming region where a source electrode and a drain electrode are to be formed on a nitride semiconductor layer formed on a substrate; forming a silicon nitride film on the surface of the nitride semiconductor layer by a plasma-enhanced chemical vapor deposition method, the silicon nitride film constituting a surface protecting sacrifice film and having a refractive index of 1.80 or more and less than 1.88 and a thickness of 100 nm or more and 500 nm or less; and heat-treating the nitride semiconductor layer on which the surface protecting sacrifice film is formed.

This normally-off mode polarization super junction GaN-based field effect transistor has an undoped GaN layer 11, an Al.sub.xGa.sub.1-xN layer 12 (0<x<1), an island-like undoped GaN layer 13, a p-type GaN layer 14, a p-type In.sub.yGa.sub.1-yN layer 15 (0<y<1), a gate electrode 16 on the p-type In.sub.yGa.sub.1-yN layer 15 and a source electrode 17 and a drain electrode 17 on the Al.sub.xGa.sub.1-xN layer 12. When the polarization charge amount of the hetero-interface between the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 11 and the hetero-interface between the Al.sub.xGa.sub.1-xN layer 12 and the undoped GaN layer 13 is denoted as N.sub.PZ and the thickness of the Al.sub.xGa.sub.1-xN layer 12 is denoted as d, N.sub.PZ d?2.64?10.sup.14 [cm.sup.?2 nm] is satisfied.

A semiconductor device, the semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; and a via disposed through the second level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.

A nitride semiconductor device includes a passivation layer which has a first opening and a second opening, and which covers an electron supply layer, a gate layer, and a gate electrode. The passivation layer includes: a first insulation layer formed on at least a portion of the electron supply layer positioned, in plan view, between the first opening and gate layer; and a second insulation layer which covers the gate layer and gate electrode, and which is formed on the electron supply layer positioned, in plan view, between the second opening and gate layer. The second insulation layer is formed from a material having a Young's modulus lower than that of the first insulation layer.

A semiconductor device may include a first inverter, a second inverter, a first access transistor, and a second access transistor. A drain electrode of the first access transistor or a source electrode of the first access transistor may be electrically connected to both an output terminal of the first inverter and an input terminal the second inverter. The drain electrode of the first access transistor may be asymmetrical to the source electrode of the first access transistor with reference to a gate electrode of the first access transistor. A drain electrode of the second access transistor or a source electrode of the second access transistor may be electrically connected to both an output terminal of the second inverter and an input terminal the first inverter.

A semiconductor device according to one embodiment the disclosure includes multiple transistors coupled in parallel to each other. Each of the transistors includes a gate electrode, a source electrode, and a drain electrode that extend in a first direction. The plurality of gate electrodes provided one by one to each of the transistors are arranged at a predetermined interval in a second direction crossing the first direction such that the following expressions (1) and (2) are satisfied:

Xi?Xi+1(1)

X1<Xn(2)

where Xi represents a center position coordinate of an i-th gate electrode of the gate electrodes in the first direction, Xi+1 represents a center position coordinate of an i+1th gate electrode of the gate electrodes in the first direction, and n represents number of the gate electrodes.

A semiconductor device capable of reducing density of threading potential without increasing a leakage current is provided. A semiconductor device including a channel layer that is included in a laminated body of a nitride semiconductor provided on a substrate, and a barrier layer that is included in the laminated body on an upper layer side with respect to the channel layer, in which the laminated body on a lower layer side with respect to the channel layer includes an n-type conversion factor that converts the nitride semiconductor into an n-type in a concentration profile having at least one or more peaks in a lamination direction of the laminated body, and a compensated area including 6?10.sup.18 cm.sup.?3 or more of a compensation factor for compensating for the n-type conversion factor is provided in the laminated body on an upper layer side with respect to peaks of the concentration profile of the n-type conversion factor.