A method for manufacturing a semiconductor device includes forming a source and region in a substrate. A core channel region is formed adjacent the source region. A barrier layer is formed adjacent the core channel region. A drain region is formed in the substrate such that the barrier layer is between the core channel region and the drain region. A first portion of a shell is formed along the core channel region. A second portion of the shell is formed along the barrier layer. The second portion of the shell includes a different material than the first portion of the shell.

A method for producing a tunnel field-effect transistor (TFET) having a source region, a channel region, and a drain region includes arranging an epitaxial layer on a silicon substrate; applying a gate arrangement having a gate electrode to the epitaxial layer, a gate dielectric being arranged between the gate electrode and the silicon substrate; forming a doped pocket region below the gate dielectric adjacent to the source region; forming a selectively silicidated region in the source region, the selectively silicidated region extending as far as to below a gate; and forming a counter-doped region doped in an opposite way to the pocket region adjacent to the pocket region in the source region by diffusion of dopants out of the silicidated region, as a result of which a tunnel junction parallel to the electric field lines of the gate electrode is achieved.

A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.

Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm.sup.3 to about 5E21 atoms per cm.sup.3. The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon). The use of a layer having a high arsenic concentration can provide improved NMOS performance in the form of abrupt junctions in the source/drain regions and highly conductive source/drain regions with negligible diffusion of arsenic into the channel region.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a gate structure on the fin-shaped structure and the STI and the fin-shaped structure directly under the gate structure includes a first epitaxial layer; forming a source region having first conductive type adjacent to one side of the gate structure; and forming a first drain region having a second conductive type adjacent to another side of the gate structure.

A method for fabrication a field-effect-transistor includes forming a plurality of fin structures on a substrate, forming a gate structure across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, forming a first doped layer, made of a first semiconductor material and doped with first doping ions, in each fin structure on one side of the corresponding gate structure, and forming a second doped layer, made of a second semiconductor material, doped with second doping ions, and having doping properties different from the first doped layer, in each fin structure on another side of the corresponding gate structure.

The invention relates to a modulation device created on a substrate (1), comprising at least one nanodiode in the form of a T fitted into a U, the channel (31) of said nanodiode being the leg of the T that is inserted into the U. The device is characterised in that it comprises at least one electrically conductive line (37) that passes over at least part of said channel (31).

An ESD protection device includes a substrate structure having a substrate, first and second fins, and first and second doped regions having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin, the second doped region includes a second portion of the substrate, a second region of the first fin adjacent to the first region and the second fin. The ESD device also includes a first gate structure on a surface portion of the first region and a surface portion of the second region of the first fin and including, from bottom to top, an interface layer on the surface portion of the first region and the surface portion of the second region of the first fin, a spacer, a high-k dielectric layer, a first work-function adjusting layer, a second work-function adjusting layer, and a gate.

A diode having a simple structure and a simple manufacturing method of the diode are provided. A diode including: a semiconductor layer having a first region and a second region having a resistance lower than a resistance of the first region; a first insulating layer having a first aperture portion and a second aperture portion and covering the semiconductor layer other than the first aperture and the second aperture, the first aperture portion exposing the semiconductor layer in the first region, the second aperture portion exposing the semiconductor layer in the second region; a first conductive layer connected to the semiconductor layer in the first aperture portion and overlapping with the semiconductor layer in the first region via the first insulating layer in a planar view; and a second conductive layer connected to the semiconductor layer in the second aperture.

A method can be used to make a semiconductor device. A number of projecting regions are formed over a first semiconductor layer that has a first conductivity type. The first semiconductor layer is located on an insulating layer that overlies a semiconductor substrate. The projecting regions are spaced apart from each other. Using the projecting regions as an implantation mask, dopants having a second conductivity type are implanted into the first semiconductor layer, so as to form a sequence of PN junctions forming diodes in the first semiconductor layer. The diodes vertically extend from an upper surface of the first semiconductor layer to the insulating layer.