A transistor including a gate region penetrating into a first gallium nitride layer, wherein a second electrically-conductive layer coats at least one of the sides of said gate region.

According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, a nitride region, and a first insulating member. The third electrode includes a first electrode portion. The first electrode portion is between the first electrode and the second electrode. The first semiconductor region includes first to sixth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The sixth partial region is between the fifth and second partial regions. The second semiconductor region includes first and second semiconductor portions. The second semiconductor portion is in contact with the fifth partial region. The nitride region includes a first nitride portion being in contact with the sixth partial region. The first insulating member includes a first insulating region between the third partial region and the first electrode portion.

A test structure for a buried gate transistor includes a substrate, a first test contact located on one side of a first transistor contact, a second test contact located on one side of a second transistor contact, and a layer buried in the substrate, having a doping greater than or equal to 10.sup.18 cm.sup.−3, and having a face which is tangent to the buried part of the gate. A first insulation structure is disposed between the first test contact and the first transistor contact and a second insulation structure is disposed between the second test contact and the second transistor contact. The first and second test contacts each have an end connected to the buried layer.

A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a p-type semiconductor layer on the barrier layer, a first layer adjacent to a first side of the p-type semiconductor layer without extending to a second side of the p-type semiconductor layer, and a second layer adjacent to the second side of the p-type semiconductor layer without extending to the first side of the p-type semiconductor layer.

The present disclosure relates to a high electron mobility transistor (HEMT) and a fabrication method thereof. The HEMT may include a substrate; a channel layer disposed on the substrate; a barrier layer disposed on the channel layer; a semiconductor gate disposed on the barrier layer; a metal gate disposed on the semiconductor gate, the metal gate having a trapezoidal cross-sectional shape; and a passivation layer directly contacting the metal gate. A first surface of the metal gate contacts a first surface of the semiconductor gate, and an edge of the first surface of the metal gate is located inside an edge of the first surface of the semiconductor gate.

A transistor is disclosed. The transistor includes a first part of a gate above a substrate that has a first width and a second part of the gate above the first part of the gate that is centered with respect to the first part of the gate and that has a second width that is greater than the first width. The first part of the gate and the second part of the gate form a single monolithic T-gate structure.

A semiconductor structure with backside through silicon vias (TSVs) is provided in the present invention, including a semiconductor substrate with a front side and a back side, multiple dummy pads set on the front side, multiple backside TSVs extending from the back side to the front side, wherein a number of the dummy pads are connected with the backside TSVs while other dummy pads are not connected with the backside TSVs, and a metal coating covering the back side and the surface of backside TSVs and connected with those dummy pads that connecting with the backside TSVs.

A method for fabricating a high electron mobility transistor (HEMT) includes the steps of first forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a compressive stress layer adjacent to one side of the p-type semiconductor layer, and then forming a tensile stress layer adjacent to another side of the p-type semiconductor layer.

A semiconductor device includes a channel layer configured to include a first nitride semiconductor containing gallium (Ga) and a first crystal dislocation density, and a barrier layer provided over a first surface side of the channel layer, and configured to include a second nitride semiconductor containing aluminum (Al) and a second crystal dislocation density, wherein the second crystal dislocation density is larger than the first crystal dislocation density.

The present disclosure relates to use of 193-nm excimer laser-based lift-off (LLO) of Al.sub.0.26Ga.sub.0.74N/GaN High-electron mobility transistors (HEMTs) with thick (t>10 μm) AlN heat spreading buffer layers grown over sapphire substrates. The use of the thick AlN heat spreading layer resulted in thermal resistance (R.sub.th) of 16 Kmm/W for as-fabricated devices on sapphire, which is lower than the value of ≈25-50 Kmm/W for standard HEMT structures on sapphire without the heat-spreaders. Soldering the LLO devices onto a copper heat sink led to a further reduction of R.sub.th to 8 Kmm/W, a value comparable to published measurements on bulk SiC substrates. The reduction in R.sub.th by LLO and bonding to copper led to significantly reduced self-heating and drain current droop. A drain current density as high as 0.9 A/mm was observed despite a marginal reduction of the carrier mobility (≈1800 to ≈1500 cm.sup.2/Vs). This is the highest drain current density and mobility reported to-date for LLO AlGaN/GaN HEMTs.