Vertical transistors and methods of manufacturing vertical transistors are disclosed. The method can include forming a stack of layers. The stack of layers includes a first sub-stack for a first transistor structure. The first sub-stack includes at least three layers of a conductive material separated by one or more layers of a dielectric material. The stack of layers includes a second sub-stack for a second transistor structure. The second sub-stack includes at least three layers of a conductive material separated by one or more layers of a dielectric material. The first and second sub-stacks are separated by dielectric materials. The method includes forming a channel opening in the stack, and providing a first channel structure that includes a semiconductive oxide material aligned with the first transistor structure. The method includes selectively forming a capping layer on the first channel structure, and providing a second channel structure within the channel opening.

A III-V device and a method for forming the device is provided. The III-V FET device includes: a device layer stack including in a bottom-up direction: a drain layer of n-type GaN, a drift layer of n-type GaN, a channel layer of p-type GaN, and a source layer; a gate extending in a top-down direction into the device layer stack and through the channel layer; and a source contact in contact with the source layer and a drain contact in contact with the drain layer; wherein the source layer is formed by a heterostructure comprising in the bottom-up direction a buffer layer of unintentionally doped GaN and a barrier layer of AlGaN.

The present disclosure provides a non-planar hole channel transistor and a fabrication method thereof. The non-planar hole channel transistor has a substrate, and a surface of the substrate has a step structure comprising a vertical surface. A non-planar channel layer is epitaxially grown laterally with the vertical surface as a core. A barrier layer is formed on the channel layer, so as to simultaneously form a two-dimensional hole gas and/or a two-dimensional electron gas at an interface between the barrier layer and the channel layer.

According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, a first insulating member, and a compound member. The third electrode includes a first electrode portion. The first electrode portion is between the first and second electrodes. The semiconductor member includes a first semiconductor region and a second semiconductor region. The first semiconductor region includes first to fifth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The second semiconductor region includes first and second semiconductor portions. The first insulating member includes a first insulating region. The first insulating region is between the third partial region and the first electrode portion. The compound member includes a first compound region. At least a part of the first semiconductor portion dose not overlap the compound member in the second direction.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity type; a second nitride semiconductor layer of a second conductivity type; an electron transport layer and an electron supply layer provided, in that order from a side on which the substrate is located, above the second nitride semiconductor layer and on an inner surface of a first opening; a gate electrode provided above the electron supply layer and covering the first opening; a source electrode provided in a second opening and connected to the second nitride semiconductor layer; a drain electrode; a third opening at an outermost edge part in a plan view of the substrate; and a potential fixing electrode provided in the third opening, the potential fixing electrode being connected to the second nitride semiconductor layer and in contact with neither the electron transport layer nor the electron supply layer.

A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a first opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; a second opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer and an electron supply layer provided along an inner face of each of the first opening and the second opening and above the second nitride semiconductor layer; a gate electrode; an anode electrode; a third opening penetrating through the electron supply layer and the electron transport layer to the second nitride semiconductor layer; a source electrode in the third opening; a drain electrode; and a cathode electrode. The anode electrode and the source electrode are electrically connected, and the cathode electrode and the drain electrode are electrically connected.

Techniques related to forming low defect density III-N films, device structures, and systems incorporating such films are discussed. Such techniques include epitaxially growing a first crystalline III-N structure within an opening of a first dielectric layer and extending onto the first dielectric layer, forming a second dielectric layer over the first dielectric layer and laterally adjacent to a portion of the first structure, and epitaxially growing a second crystalline III-N structure extending laterally onto a region of the second dielectric layer.

The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the metal gate electrode and the source metal electrode only exist in the cell region, and the passivation layer of the terminal region extends upwards and is wrapped outside the channel layer. This structure can increase a threshold voltage of the device, improve the blocking characteristics of the device and reduce the size of a gate capacitance.

A semiconductor device includes a substrate including a first region and a second region, a first active pattern on the first region, a first gate structure having a first width in the first direction, on the first active pattern, a first epitaxial pattern disposed in the first active pattern on a side surface of the first gate structure, a second active pattern on the second region, a second gate structure having a second width greater than the first width in the first direction, on the second active pattern and a second epitaxial pattern disposed in the second active pattern on a side surface of the second gate structure. Each of the first epitaxial pattern and the second epitaxial pattern includes silicon germanium (SiGe), and a first Ge concentration of the first epitaxial pattern is lower than a second Ge concentration of the second epitaxial pattern.

Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.