Provided are a semiconductor device and a method for manufacturing same. The device comprises: a substrate, a first insulating layer on the substrate, a plurality of trenches formed in the substrate, a nucleation layer arranged on one side wall of each trench, and a first semiconductor layer formed along the trenches by means of the nucleation layer. The present disclosure facilitates the achievement of one of the following effects: achieving a high height-width ratio and a high integration density, reducing an on-resistance, improving a threshold voltage, achieving a normally-off state, and providing a semiconductor device that has a high power and a high reliability, is suitable for a planarization process, is provided with an easy preparation method, and reduces costs.

A semiconductor device and a method of fabricating the same are proposed. The semiconductor device includes a plurality of hole-channel Group III nitride devices and a plurality of electron-channel Group III nitride devices. In the above, the hole-channel Group III nitride devices and the electron-channel Group III nitride devices are arranged in correspondence with each other. The electron-channel Group III nitride device has a fin-shaped channel, and a two-dimensional hole gas and/or a two-dimensional electron gas can be simultaneously formed at an interface between a compound semiconductor layer and a nitride semiconductor layer.

An integrated circuit structure includes a first semiconductor fin extending horizontally in a length direction and including a bottom portion and a top portion above the bottom portion, a bottom transistor associated with the bottom portion of the first semiconductor fin, a top transistor above the bottom transistor and associated with the top portion of the first semiconductor fin, and a first vertical diode. The first vertical diode includes: a bottom region associated with at least the bottom portion of the first semiconductor fin, the bottom region including one of n-type and p-type dopant; a top region associated with at least the top portion of the first semiconductor fin, the top region including the other of n-type and p-type dopant; a bottom terminal electrically connected to the bottom region; and a top terminal electrically connected to the top region at the top portion of the first semiconductor fin.

A method for forming a high-electron mobility transistor is disclosed. A substrate is provided. A buffer layer is formed over the substrate. A GaN channel layer is formed over the buffer layer. An AlGaN layer is formed over the GaN channel layer. A GaN source layer and a GaN drain layer are formed on the AlGaN layer within a source region and a drain region, respectively. A gate recess is formed in the AlGaN layer between the source region and the drain region. A p-GaN gate layer is then formed in and on the gate recess.

A normally-off vertical nitride semiconductor transistor device with low threshold voltage variation includes a drift layer containing a nitride semiconductor, a channel region electrically connected to the drift layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode. The gate insulating film includes at least a first insulating film located at the channel region side, a second insulating film located at the gate electrode side, and a third insulating film between the second insulating film and the gate electrode, wherein the second insulating film has charge traps with energy levels located inside the band gaps of both the first and third insulating films, and the threshold voltage is adjusted by charges accumulated in the charge traps. The threshold voltage is used to block flowing current by substantially eliminating conduction carriers of the channel region by voltage applied to the gate electrode.

A GaN-based power transistor including: a stack of layers in a vertical direction (z), the stack including, from an upper surface of the stack: a first AlGaN-based barrier), a GaN-based layer, and a second AlGaN-based barrier; and a gate pattern including: a metal gate, and a gate dielectric electrically insulating the metal gate from the stack, the metal gate being in contact with a bottom part and a wall part of the gate dielectric, the gate pattern passing through the first AlGaN-based barrier, then totally passing through the GaN-based layer and at least partially through the second AlGaN-based barrier, in the vertical direction (z), such that the second AlGaN-based barrier has a concentration of aluminium [Al]2 of less than or equal to 8% at.

A nitride semiconductor device includes: a substrate; a nitride semiconductor layer above the substrate; a high-resistance layer above the nitride semiconductor layer; a p-type nitride semiconductor layer above the high-resistance layer; a first opening penetrating through the p-type nitride semiconductor layer and the high-resistance layer to the nitride semiconductor layer; an electron transport layer and an electron supply layer covering an upper portion of the p-type nitride semiconductor layer and the first opening; a gate electrode above the electron supply layer; a source electrode in contact with the electron supply layer; a second opening penetrating through the electron supply layer and the electron transport layer to the p-type nitride semiconductor layer; a potential fixing electrode in contact with the p-type nitride semiconductor layer at a bottom part of the second opening; and a drain electrode.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor layer, a second semiconductor layer, and a first insulating layer. A position of the third electrode in a first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction. The first semiconductor layer includes Al.sub.x1Ga.sub.1-x1N and includes a first partial region, a second partial region, and a third partial region. The second semiconductor layer includes Al.sub.x2Ga.sub.1-x2N. A portion of the second semiconductor layer is between the third partial region and the third electrode in the second direction. The first insulating layer includes a first insulating region. The first insulating region is between the third electrode and the portion of the second semiconductor layer in the second direction.

The present disclosure provides a driving circuit, a driving IC, and a driving system, relating to the technical field of electronic circuits. The driving circuit comprises a control module and a driving signal output module, the control module is electrically connected to the driving signal output module, and the driving signal output module is configured to be electrically connected to a to-be-driven device, wherein the driving signal output module comprises at least two transistors, and the at least two transistors are epitaxially grown on the same substrate; and the control module is configured to control a closed state of the at least two transistors, so as to control an operation state of the to-be-driven device.

A semiconductor device manufacturing method of embodiments includes: performing first ion implantation implanting an element of either carbon (C) or oxygen (O) into a nitride semiconductor layer; performing second ion implantation implanting hydrogen (H) into the nitride semiconductor layer; forming a coating layer on a surface of the nitride semiconductor layer; performing a first heat treatment; removing the coating layer; and performing a second heat treatment.