A manufacturing method for a LDMOS semiconductor device may include steps of forming a P-type layer on a P-type substrate; forming a P-type body region and an N-type well under the P-type layer; forming a field oxide on the P-type layer; forming a gate oxide on the P-type body region and field oxide; forming a gate polysilicon on top of the gate oxide; depositing a gate metal silicide on top of the gate polysilicon; depositing a thin film on top of the field oxide, P-type body region and gate silicide; forming a dielectric layer on top of the thin film; forming a first trench in the dielectric layer; forming a second trench underneath the first trench; depositing a metal layer on top of the dielectric layer and filling into the first and second trenches; and removing the metal on top of the dielectric layer.

Disclosed is a technique capable of reducing loss at the time of switching in a diode. A diode disclosed in the present specification includes a cathode electrode, a cathode region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, an anode region made of a second conductivity type semiconductor, an anode electrode made of metal, a barrier region formed between the drift region and the anode region and made of a first conductivity type semiconductor having a concentration higher than that of the drift region, and a pillar region formed so as to connect the barrier region to the anode electrode and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region. The pillar region and the anode are connected through a Schottky junction.

Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.

A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material over the substrate. Source and drain contacts are formed partially over the 2D material. A first dielectric layer is formed at least partially over the channel structure and at least partially over the source and drain contacts. The first dielectric layer is configured to trap charge carriers. A second dielectric layer is formed over the first dielectric layer, and a gate electrode is formed over the second dielectric layer.

A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material over the substrate. Source and drain contacts are formed partially over the 2D material. A first dielectric layer is formed at least partially over the channel structure and at least partially over the source and drain contacts. The first dielectric layer is configured to trap charge carriers. A second dielectric layer is formed over the first dielectric layer, and a gate electrode is formed over the second dielectric layer.

The present disclosure provides a multi-functional electronic device with a black phosphorous-based single channel, wherein the device comprises: a black phosphorous-based single channel layer including a horizontal arrangement of a first semiconductor region and a second semiconductor region to define a horizontal junction therebetween, wherein the second semiconductor region has a lower hole-carrier density than the first semiconductor region; a first electrode connected to the first semiconductor region; a second electrode spaced from the first electrode and connected to the second semiconductor region; an ionic gel layer disposed on the first semiconductor region; and a gate electrode for receiving a gate voltage to generate an electric field in the channel layer.

Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.

A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.

According to one embodiment, a semiconductor device includes a first element. The first element includes a first conductive member, a second conductive member, a first semiconductor member, a third conductive member, and a third conductive member wiring. The first conductive member includes a first conductive portion including a first face and a second conductive portion including a second face. The second conductive member includes a third conductive portion including a third face and a fourth conductive portion including a fourth face. The fourth conductive portion includes a facing conductive portion. The first semiconductor member is of a first conductive type. The first semiconductor member includes a first partial region, a second partial region and a third partial region. The third partial region includes a facing face facing the facing conductive portion. The third conductive member wiring is electrically connected to the third conductive member.