A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

Disclosed are exemplary embodiments of compressible foamed thermal interface materials. Also disclosed are methods of making and using compressible foamed thermal interface materials.

A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 μm from each other to enable contact or direct-bonding between pads and vias with diameters under 5 μm at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives. A nanowire forming technique creates a nanoporous layer on conductive pads, creates nanowires within pores of the nanoporous layer, and removes at least part of the nanoporous layer to reveal a layer of nanowires less than 1 μm in height for direct bonding.

A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

Disclosed are exemplary embodiments of compressible foamed thermal interface materials. Also disclosed are methods of making and using compressible foamed thermal interface materials.

A method of manufacturing a display device, includes: providing an adhesive tape including: an adhesive conductive layer on a base film, a cutting width corresponding to a width of an adhesive tape attaching area of a substrate and provided in plurality including cutting widths adjacent to each other along the base film, and an interval between the cutting widths adjacent to each other; within the interval, providing a plurality of half-cuts in the adhesive tape, to provide a multi-cut adhesive tape; and pressing the multi-cut adhesive tape to the substrate, at a first portion of the multi-cut adhesive tape which corresponds to the cutting width, to separate the first portion of the multi-cut adhesive tape from the base film and attach the first portion of the multi-cut adhesive tape to the substrate at the adhesive tape attaching area thereof.

A method of manufacturing a display device, includes: providing an adhesive tape including: an adhesive conductive layer on a base film, a cutting width corresponding to a width of an adhesive tape attaching area of a substrate and provided in plurality including cutting widths adjacent to each other along the base film, and an interval between the cutting widths adjacent to each other; within the interval, providing a plurality of half-cuts in the adhesive tape, to provide a multi-cut adhesive tape; and pressing the multi-cut adhesive tape to the substrate, at a first portion of the multi-cut adhesive tape which corresponds to the cutting width, to separate the first portion of the multi-cut adhesive tape from the base film and attach the first portion of the multi-cut adhesive tape to the substrate at the adhesive tape attaching area thereof.

Disclosed herein is a method of forming an electrical connecting structure having nano-twins copper. The method includes the steps of (i) forming a first nano-twins copper layer including a plurality of nano-twins copper grains; (ii) forming a second nano-twins copper layer including a plurality of nano-twins copper grains; and (iii) joining a surface of the first nano-twins copper layer with a surface of the second nano-twins copper layer, such that at least a portion of the first nano-twins copper grains grow into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains grow into the first nano-twins copper layer. An electrical connecting structure having nano-twins copper is provided as well.

A method for manufacturing an electronic component includes preparing a mounting substrate provided with a first region to mount an electronic component thereon and a second region having conductivity, covering the second region with resin, applying a metal paste on the first region, mounting the electronic component on the first region with the metal paste, and removing the resin covering the second region. The mounting includes heating the mounting substrate to cure the metal paste with the electronic components being placed on the metal paste applied on the first region. The resin peeled from the second region by the heating is removed in the removing.

A silicon carbide semiconductor device including a semiconductor substrate containing silicon carbide, a contact electrode, which is a silicide layer containing nickel, provided on a surface of the semiconductor substrate and forming an ohmic contact with the semiconductor substrate, and a metal connection layer provided on a surface of the contact electrode. The metal connection layer has a stacked structure in which on the surface of the contact electrode, a titanium layer, a nickel layer, and a gold layer are sequentially stacked. The titanium layer includes a carbon diffusion layer formed along an interface between the titanium layer and the contact electrode, a concentration of carbon being higher in the carbon diffusion layer than in a portion of the titanium layer other than the carbon diffusion layer. The titanium layer, the nickel layer and the gold layer have thicknesses of 100 nm to 300 nm, 1000 nm to 1500 nm, and 20 nm to 200 nm, respectively.