A method for bonding a first substrate to a second substrate including the steps of: making contact of a first contact area of the first substrate with a second contact area of the second substrate, which second area is aligned parallel to the first contact area, as a result of which a common contact area is formed; and producing a bond interconnection between the first substrate and the second substrate outside the common contact area. The invention also relates to a corresponding device and a substrate composite of a first substrate and a second substrate, in which a first contact area of the first substrate with a second contact area of the second substrate, which second area is aligned parallel to the first contact area, forms a common contact area, outside the common contact area there being a bond interconnection between the first substrate and the second substrate.

A semiconductor package includes a carrier, a package module and a second package body. The package module is disposed on the carrier and includes a first substrate, a first electronic element, a first conductive wire and a first package body. The first substrate has a first electrical surface facing the carrier and a second electrical surface opposite to the first electrical surface. The first electronic element is disposed on the first electrical surface. The first conductive wire connects the electronic element with the first electrical surface of the first substrate. The first package body encapsulates the first electrical surface, the first electronic element and the first solder wire. The second package body encapsulates the package module and a portion of the carrier.

An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-to-oxide edge bonding. A chip-to-chip interconnect structure electrically couples the first IC chip and the second IC chip.

A semiconductor device includes a redistribution structure, an integrated circuit package attached to a first side of the redistribution structure and a core substrate coupled to a second side of the redistribution structure with a first conductive connector and a second conductive connector. The second side is opposite the first side. The semiconductor device further includes a top layer of the core substrate including a dielectric material and a chip disposed between the redistribution structure and the core substrate. The chip is interposed between sidewalls of the dielectric material.

A semiconductor device includes a redistribution structure, an integrated circuit package attached to a first side of the redistribution structure and a core substrate coupled to a second side of the redistribution structure with a first conductive connector and a second conductive connector. The second side is opposite the first side. The semiconductor device further includes a top layer of the core substrate including a dielectric material and a chip disposed between the redistribution structure and the core substrate. The chip is interposed between sidewalls of the dielectric material.

A bus bar for a power semiconductor module arrangement includes a first end, and a second end. The first end is configured to be arranged inside a housing of the power semiconductor module arrangement. The second end is configured to be arranged outside of the housing and to be electrically contacted by an external bus bar. The second end includes a structured area that includes a plurality of protrusions. A height of each of the protrusions is between 10 m and 1000 m.