Embodiments of the present disclosure describe novel qubit device packages, as well as related computing devices and methods. In one embodiment, an exemplary qubit device package includes a qubit die and a package substrate, where the qubit die is coupled to the package substrate using one or more preforms. In particular, a single preform may advantageously be used to replace a plurality of individual contacts, e.g. a plurality of individual solder bumps, electrically coupling the qubit die to the package substrate. Such packages may reduce design complexity and undesired coupling, and enable inclusion of larger numbers of qubits in a single qubit die.

A semiconductor device includes a wiring board including first and second surfaces opposite to each other, a first semiconductor element on the first surface side of the wiring board, a second semiconductor element adjacent to the first semiconductor element on the first surface side of the wiring board, a first resin composition on the first surface side of the wiring board, and a second resin composition that covers the first and second semiconductor elements and the first resin composition. The first resin composition includes a first part between the first surface of the wiring board and a surface of the first semiconductor element facing the first surface, and a second part contacting a first side surface of the second semiconductor element facing the first semiconductor element.

A circuit-board-assembly includes a printed-circuit-board, an integrated-circuit-die, a ball-grid-array, a barrier-material, and an adhesive-material. The printed-circuit-board includes a mounting-surface that defines a plurality of contact-pads and a continuous-trace that interconnects a selected-group of the contact-pads. The integrated-circuit-die includes an electrical-circuit having a plurality of solder-pads. The ball-grid-array includes a plurality of solder-balls interposed between the contact-pads and the solder-pads. The plurality of solder-balls establish electrical communication between the electrical-circuit and the contact-pads. The barrier-material is located between a string of solder-balls that are attached to the selected-group of the contact-pads to create a barrier. The barrier segregates an underfill-region from a non-underfill-region between the printed-circuit-board and the integrated-circuit-die. The barrier is in direct-contact with the string of the solder-balls, the integrated-circuit-die, and the continuous-trace. The adhesive-material is in direct contact with a portion of the underfill-region and the barrier prevents the adhesive-material from encroaching upon the non-underfill-region.

A mounting structure includes a bonding material (106) that bonds second electrodes (104) of a circuit board (105) and bumps (103) of a semiconductor package (101), the bonding material (106) being surrounded by a first reinforcing resin (107). Moreover, a portion between the outer periphery of the semiconductor package (101) and the circuit board (105) is covered with a second reinforcing resin (108). Even if the bonding material (106) is a solder material having a lower melting point than a conventional bonding material, high drop resistance is obtained.

A mounting structure includes a bonding material (106) that bonds second electrodes (104) of a circuit board (105) and bumps (103) of a semiconductor package (101), the bonding material (106) being surrounded by a first reinforcing resin (107). Moreover, a portion between the outer periphery of the semiconductor package (101) and the circuit board (105) is covered with a second reinforcing resin (108). Even if the bonding material (106) is a solder material having a lower melting point than a conventional bonding material, high drop resistance is obtained.

A method for bonding a first substrate to a second substrate including the steps of: making contact of a first contact area of the first substrate with a second contact area of the second substrate, which second area is aligned parallel to the first contact area, as a result of which a common contact area is formed; and producing a bond interconnection between the first substrate and the second substrate outside the common contact area. The invention also relates to a corresponding device and a substrate composite of a first substrate and a second substrate, in which a first contact area of the first substrate with a second contact area of the second substrate, which second area is aligned parallel to the first contact area, forms a common contact area, outside the common contact area there being a bond interconnection between the first substrate and the second substrate.

An electronic component has a circuit board with a main surface, a chip having a sensor facing the main surface, bump electrodes disposed between the main surface and the chip so as to be placed inside of the edges of the chip in a plan view of the main surface, a dam provided between the main surface and the chip so as to extend at least from the edges of the chip to outer positions of the bump electrodes in a plan view of the main surface, and an under-fill material provided at least in a clearance between the dam and the chip. Between the main surface and the sensor, a space is formed in a region enclosed by the bump electrodes in a plan view of the main surface. The under-fill material is disposed outside of the space in a plan view of the main surface.

An electronic component has a circuit board with a main surface, a chip having a sensor facing the main surface, bump electrodes disposed between the main surface and the chip so as to be placed inside of the edges of the chip in a plan view of the main surface, a dam provided between the main surface and the chip so as to extend at least from the edges of the chip to outer positions of the bump electrodes in a plan view of the main surface, and an under-fill material provided at least in a clearance between the dam and the chip. Between the main surface and the sensor, a space is formed in a region enclosed by the bump electrodes in a plan view of the main surface. The under-fill material is disposed outside of the space in a plan view of the main surface.

An integrated device package is disclosed. The package can include a carrier, such as first integrated device die, and a second integrated device die stacked on the first integrated device die. The package can include a buffer layer which coats at least a portion of an exterior surface of the first integrated device die and which is disposed between the second integrated device die and the first integrated device die. The buffer layer can comprise a pattern to reduce transmission of stresses between the first integrated device die and the second integrated device die.

An electronic device is provided. The electronic device includes a photonic component, a plurality of optical elements, a connection layer, and a cover. The photonic component defines a predetermined region. The optical elements are disposed at the predetermined region and configured to optically couple with the photonic component. The connection layer is connected to the photonic component and the optical elements. The cover is configured to protect the optical elements and configured to vent.