In an embodiment, a semiconductor apparatus comprises: a semiconductor chip, a substrate, and a bonding layer located between the semiconductor chip and the substrate that bonds the semiconductor chip and the substrate, wherein the bonding layer comprises sintered metal that comprises a plurality of voids, and wherein at least a portion of the plurality of voids are filled with a specific material having fluidity at a temperature higher than a preset temperature and is curable after being heated and melted.

According to one embodiment, a semiconductor device includes a first semiconductor element having a first surface, a second semiconductor element having a lower surface bonded to the first surface of the first semiconductor element, a gel-like silicone that covers an upper surface of the second semiconductor element, and a resin portion that covers the gel-like silicone and the first surface of the first semiconductor element.

Anodic bonding method are disclosed. In one embodiment, an anodic bonding method may include: (1) providing a first substrate (100) having a semiconductor material; (2) providing a second substrate (200) having a bondable passivation material and contact vias (210); (3) contacting the first substrate and the second substrate (100, 200); (4) providing a resistance layer (300, 220) on the second substrate (200); and (5) applying a potential between the resistance layer and the first substrate.

A semiconductor device comprising a first substrate (100) including silicon may include a bondable passivation (200) made of a bondable material, especially a glass material; at least one contact via (210) extending through the passivation and contacting a region of the first substrate (100); an interface (204) created by anodic bonding between the substrate including silicon and the bondable passivation (200), wherein silicon-oxygen-silicon bonds are formed in the interface in order to provide adhesion between the passivation (200) and the substrate (100)

A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

A ceramic circuit substrate is suitable for silver nanoparticle bonding of semiconductor elements and has excellent close adhesiveness with a power module sealing resin. A ceramic circuit substrate has a copper plate bonded, by a braze material, to both main surfaces of a ceramic substrate including aluminum nitride or silicon nitride, the copper plate of at least one of the main surfaces being subjected to silver plating, wherein: the copper plate side surfaces are not subjected to silver plating; the thickness of the silver plating is 0.1 m to 1.5 m; and the arithmetic mean roughness Ra of the surface roughness of the circuit substrate after silver plating is 0.1 m to 1.5 m.

A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.

Bonded surfaces are formed by adhering first nanorods and second nanorods to respective first and second surfaces. The first shell is formed on the first nanorods and the second shell is formed on the second nanorods, wherein at least one of the first nanorods and second nanorods, and the first shell and the second shell are formed of distinct metals. The surfaces are then exposed to at least one condition that causes the distinct metals to form an alloy, such as eutectic alloy having a melting point below the temperature at which the alloy is formed, thereby bonding the surfaces upon which solidification of the alloy.

Concepts as well as arrangements are suggested, according to which a bond is enabled by anodic bonding between a glass substrate (200) having contact vias (210) and a substrate (100) including a semiconductor. For this purpose, a cover of the contact vias (210) is provided during the anodic bonding method such that process conditions are created that achieve a reliable and robust bonding of the substrates. A high resistance can be provided in the region of the contact vias (210). The arrangement for contacting the semiconductor device to the silicon substrate (100) having at least one contact via (210) extending through the passivation in order to contact a region of the first substrate (100).

A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.