A method of forming a wire loop in connection with a semiconductor package is provided. The method includes the steps of: (1) providing package data related to the semiconductor package to a wire bonding machine; (2) providing at least one looping control value related to a desired wire loop to the wire bonding machine, the at least one looping control value including at least a loop height value related to the desired wire loop; (3) deriving looping parameters, using an algorithm, for forming the desired wire loop; (4) forming a first wire loop on the wire bonding machine using the looping parameters derived in step (3); (5) measuring actual looping control values of the first wire loop formed in step (4) corresponding to the at least one looping control value; and (6) comparing the actual looping control values measured in step (5) to the at least one looping control value provided in step (2).

Provided is a bonding wire capable of reducing the occurrence of defective loops. The bonding wire includes: a core material which contains more than 50 mol % of a metal M; an intermediate layer which is formed over the surface of the core material and made of Ni, Pd, the metal M, and unavoidable impurities, and in which the concentration of the Ni is 15 to 80 mol %; and a coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities. The concentration of the Pd in the coating layer is 50 to 100 mol %. The metal M is Cu or Ag, and the concentration of Ni in the coating layer is lower than the concentration of Ni in the intermediate layer.

A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

This wire bonding apparatus has a capillary, a movement mechanism moving the capillary, and a control unit controlling driving of the movement mechanism. The control unit at least causes execution of: a first process (trajectory a) of lowering the capillary, after a FAB is formed, to pressure bonding height at a first bonding point to form a pressure bonded ball and a column part at the first bonding point; a second process (trajectory b) of moving the capillary horizontally at the pressure bonding height after execution of the first process to scarp off the column part by the capillary; and a third process (trajectory c-k) of repeating a pressing operation at least once after execution of the second process, the pressing operation involving moving the capillary forward and lowering the capillary temporarily during movement so that the capillary presses down on a wire portion positioned over the pressure bonded ball.

A semiconductor package includes a substrate that includes a bonding pad, a first semiconductor chip disposed on the substrate, a second semiconductor chip disposed on a top surface of the first semiconductor chip that is opposite to the substrate, a chip pad disposed on the top surface of the first semiconductor chip, and a bonding wire that connects the chip pad to the bonding pad. The bonding wire includes a first upward protrusion and a second upward protrusion that are convexly curved in a direction away from the substrate. The second semiconductor chip has a first side surface between the first upward protrusion and the second upward protrusion.

Provided is a wire shape measurement device of a semiconductor device comprising a substrate, a semiconductor element, and a wire connecting an electrode of the semiconductor element to an electrode of the substrate. The wire shape measurement device comprises: cameras that capture two-dimensional images of the semiconductor device; and a control unit that examines the shape of the wire based on the two-dimensional images of the semiconductor device acquired by the cameras. The control unit performs pattern matching using information on the position at which the wire is connected to the substrate or the semiconductor element and thickness information of the wire, and by utilizing the pattern matching, the control unit: generates a three-dimensional image of the wire from the two-dimensional images of the semiconductor device acquired by the cameras; and performs shape measurement of the wire based on the generated three-dimensional image of the wire.

An optical transmitter capable of significantly suppressing a fluctuation in frequency response characteristics due to a fabrication error in internal wire length while reducing a subcarrier size of a module of the optical transmitter is provided. The optical transmitter includes: a subcarrier on which an RF wiring board, a modulated laser chip, and a terminating resistor are mounted and which has a ground pad on an upper surface thereof; and a wire for electrically connecting at least the RF wiring board and the modulated laser chip to each other, wherein the RF wiring board and the modulated laser chip are arranged in a width direction of the subcarrier, and a length of the wire in an electric path which starts at the RF wiring board, passes through the terminating resistor, and reaches the ground pad is 0.5 to 1.5 mm or an inductance of the wire is 0.4 to 1.2 nH.

A sensor package structure is provided. The sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of electrical connection members electrically connecting the sensor chip to the substrate, a supporting adhesive layer formed on the sensor chip, and a light-permeable sheet disposed on the supporting adhesive layer. Each of the electrical connection members includes a head solder disposed on a connecting pad of the sensor chip, a wire having a first end and a second end, and a tail solder. The first end of the wire extends from the head solder so as to connect the second end onto a soldering pad of the substrate, and the wire has a first bending portion arranged adjacent to the head solder. The head solder and the first bending portion of each of the electrical connection members are embedded in the supporting adhesive layer.

A semiconductor device includes an insulated circuit board including a circuit pattern, a semiconductor chip on the circuit pattern, a wire connected to the semiconductor chip, an external connection terminal including a leg portion extending in a direction perpendicular to a front surface of the circuit pattern and a terminal portion electrically connected to the leg portion, and a case including a frame portion which surrounds an insulated circuit board and a beam portion bonded to an external connection terminal and overlapping at least a part of a wire in a plan view of the semiconductor device, and a sealing member with which the case is filled, which seals a front surface of the insulated circuit board, a semiconductor chip, the wire, and a back surface of the beam portion, and which is exposed in the plan view from a gap between a leg portion and the beam portion.

A semiconductor includes: a substrate; a circuit pattern on the substrate, and including a first region, a second region located away from the first region, and a third region between the first region and the second region; a first chip disposed in the second region and including a diode; a second chip disposed in the third region, the second chip including a vertical transistor having a source pad disposed on a surface opposite to a surface facing the third region in a thickness direction of the substrate, and a gate pad disposed at a position different from the source pad; a first wire including a first bonded portion bonded to the first region, a second bonded portion bonded to the second chip, and a third bonded portion bonded to the first chip; and a second wire arranged to be adjacent to the first wire with the gate pad sandwiched therebetween.