A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.

An electronic device is provided, the electronic device includes a driving substrate (13), the driving substrate includes a plurality of circular grooves and a plurality of rectangular grooves, and a plurality of disc-shaped electronic components, at least one disc-shaped electronic component is disposed in at least one circular groove, an alignment element positioned on a top surface of the at least one disc-shaped electronic component, a diameter of the at least one disc-shaped electronic component is defined as R, a diameter of the alignment element is defined as r, a width of at least one rectangular groove among the rectangular grooves is defined as w, and a height of the at least one rectangular groove is defined as H, and the disc-shaped electronic component and the rectangular groove satisfy the condition of (R+r)/2>(w.sup.2+H.sup.2).sup.1/2.

A semiconductor package may include a semiconductor chip on a package substrate. The semiconductor package may include a plurality of conductive connections connecting the semiconductor chip to the package substrate may be disposed, a plurality of towers which are apart from one another and each include a plurality of memory chips may be disposed, wherein a lowermost memory chip of each of the plurality of towers overlaps the semiconductor chip from a top-down view. The semiconductor package further includes a plurality of adhesive layers be attached between the lowermost memory chip of each of the plurality of towers and the semiconductor chip.

Packaging method for forming the panel-level chip device is provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

A semiconductor device includes an insulating substrate, a wiring, a semiconductor chip and a resin layer. The wiring is provided on the insulating substrate. The wiring board includes (i) an insulating material and (ii) a pad exposed relative to the insulating material and electrically connected to the wiring. A height of the insulating material in a vertical direction of the wiring board varies along the wiring board. The semiconductor chip includes a bump connected to the pad on a first surface of the semiconductor chip. The resin layer covers a periphery of the bump between the wiring board and the semiconductor chip.

A regulating jig that includes one end, the other end, and a groove having opposite regulating surfaces formed therein, between the one end and the other end is set on a positioning jig. At this time, the regulating surfaces are positioned at sides of the regulating member entering the groove, and the one end and the other end of the regulating jig are positioned on respective opposite sides of the opening edge of an opening area of the positioning jig. Then, a base substrate, a solder sheet, and an insulated circuit substrate are heated to bond the insulated circuit substrate to the base substrate.

A tolerance compensation element is for circuit configurations having a DCB (direct copper bonded) substrate and a PCB (printed circuit board). A circuit configuration further includes the tolerance compensation element. A tolerance compensation element is positioned in a targeted manner between the DCB substrate and PCB in a gap A for the contact-connection of components on the DCB substrate via additive manufacturing and is formed so as to close the gap.

A method of manufacturing a light source device includes: disposing bumps containing a first metal on a first substrate which is thermally conductive; disposing a bonding member on the bumps, the bonding member containing Au—Sn alloy; disposing a light emitting element on the bumps and the bonding member; and heating the first substrate equipped with the bumps, the bonding member, and the light emitting element.

A display device is disclosed. The display device includes a substrate having a plurality of pixels, wherein each of the plurality of pixels includes at least one light emitting chip, and a structure on one side of at least one of the plurality of pixels. A base material of the light emitting chip is the same as a base material of the structure.

A semiconductor device having a capillary flow structure for a direct chip attachment is provided herein. The semiconductor device generally includes a substrate and a semiconductor die having a conductive pillar electrically coupled to the substrate. The front side of the semiconductor die may be spaced a distance apart from the substrate forming a gap. The semiconductor device further includes first and second elongate capillary flow structures projecting from the front side of the semiconductor die at least partially extending toward the substrate. The first and second elongate capillary flow structures may be spaced apart from each other at a first width configured to induce capillary flow of an underfill material along a length of the first and second elongate capillary flow structures. The first and second capillary flow structures may include pairs of elongate capillary flow structures forming passageways therebetween to induce capillary flow at an increased flow rate.