H01L2224/8314

APPLICATION AND FASTENING OF A DEFINED NUMBER OF INDIVIDUAL ELEMENTS TO A SUBSTRATE WEB
20220055853 · 2022-02-24 ·

The invention relates to a method for applying and attaching a defined number n of individual elements to a defined number m of predefined positions on a surface of a moving substrate web. The invention further relates to a moving substrate web onto which a defined number n of individual elements are to be applied and attached to a defined number m of predefined positions on a surface of a moving substrate web. According to the invention, an adhesive is applied to the surface of the substrate web at each of the predefined positions so that respectively at least one individual element can be attached at respectively one predefined position, and no adhesive is applied outside the predefined positions.

Stacked semiconductor package and packaging method thereof

A stacked semiconductor package has a substrate, a first chip, at least one spacer, a second chip and an encapsulation. The first chip and the second chip are intersecting stacked on the substrate. The at least one spacer is stacked on the substrate to support the second chip. The encapsulation is formed to encapsulate the substrate, the first chip, the at least one spacer and the second chip. The at least one spacer is made of the material of the encapsulation. Therefore, the adhesion between the at least one spacer and the encapsulation is enhanced to avoid the delamination during the reliability test and enhances the reliability of the stacked semiconductor package.

Semiconductor device

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.

Printed circuit board

Provided is a printed circuit board including: an insulating layer; electronic devices embedded in the insulating layer; and an adhesive layer for fixing the electronic devices.

SEMICONDUCTOR DEVICE ASSEMBLIES AND SYSTEMS WITH INTERNAL THERMAL BARRIERS AND METHODS FOR MAKING THE SAME

Semiconductor device assemblies are provided with a layer of thermal barrier material between a first semiconductor device (e.g., a logic die or other heat-generating device) and a second semiconductor device (e.g., a memory die or other device whose performance may be improved in a lower-temperature environment). The layer of thermal barrier material can reduce the conduction of the heat generated by the first semiconductor device towards the second semiconductor device. The assemblies can also include one or more thermally conductive structures disposed in the substrate under the first semiconductor device and configured to conduct the heat from the first semiconductor device out of the semiconductor device assembly.

Method to provide die attach stress relief using gold stud bumps
09754914 · 2017-09-05 · ·

An integrated circuit is attached to a substrate with a controlled stand-off height, by mounting a plurality of stud bumps of the controlled stand-off height to the substrate at predetermined locations, placing adhesive dots over the stud bumps, placing the integrated circuit on the substrate over the adhesive dots, and applying downward pressure on the integrated circuit until the integrated circuit is in mechanical contact with the stud bumps.

Method to provide die attach stress relief using gold stud bumps
09754914 · 2017-09-05 · ·

An integrated circuit is attached to a substrate with a controlled stand-off height, by mounting a plurality of stud bumps of the controlled stand-off height to the substrate at predetermined locations, placing adhesive dots over the stud bumps, placing the integrated circuit on the substrate over the adhesive dots, and applying downward pressure on the integrated circuit until the integrated circuit is in mechanical contact with the stud bumps.

THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH THREE DIMENSIONAL INTEGRATION AND METHOD OF MAKING THE SAME
20170243803 · 2017-08-24 ·

A thermally enhanced semiconductor assembly with three dimensional integration includes a semiconductor chip electrically coupled to a wiring board by bonding wires. A heat spreader that provides an enhanced thermal characteristic for the semiconductor chip is disposed in a through opening of a wiring structure. Another wiring structure disposed on the heat spreader not only provides mechanical support, but also allows heat spreading and electrical grounding for the heat spreader by metallized vias. The bonding wires provide electrical connections between the semiconductor chip and the wiring board for interconnecting the semiconductor chip to terminal pads provided in the wiring board.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING BASE AND SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE
20170229415 · 2017-08-10 · ·

In a method of manufacturing a semiconductor device of one embodiment, support members and a film which is formed of a paste containing metal particles and surrounds the support members are provided above a surface of a base. Then a semiconductor element is provided above the support members and the film. Subsequently, the film is sintered to join the base and the semiconductor element. The support members are formed of a metal which melts at a temperature equal to or below a sintering temperature of the metal particles contained in the paste. The support members support the semiconductor element after the semiconductor element is provided above the support members and the film.

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
20170256473 · 2017-09-07 ·

A semiconductor package structure and manufacturing method thereof are provided. Firstly, a first surface mounting unit, a first printed circuit board, and a second printed circuit board are provided. The first surface mounting unit includes a first chip and a first conductive frame, and the first conductive frame has a first carrier board and a first metal member connected to the first carrier board. A first side of the first chip is electrically connected to the first carrier board of the first conductive frame. A second side of the first chip and the first metal member are connected to the first circuit board by a first pad and a second pad respectively. The second circuit board is connected to the first carrier board and hence, the first surface mounting unit is located between the first circuit board and the second circuit board.