A formulation for a wafer dicing process comprises 1.0 to 1.5 mass % of a partially saponified polyvinyl alcohol having a polymerization degree of 200 to 400 and a saponification degree of 75 to 85 mol %; 0.4 to 0.6 mass % of polyoxyethylene-polyoxypropylene glycol ether having a number average molecular weight of 10,000 to 20,000 with a polymerization ratio of polyoxyethylene to polyoxypropylene of 75:25 to 85:15; and pure water (all mass % based on 100 mass % of formulation). The formulation is used in the form of a processing solution obtained by diluting it 10,000 to 100,000 times by pure water and flowing it on a dicing blade in a wafer dicing process to effectively remove dicing offcuts from the wafer and minute pieces of adhesive released from an adhesive layer of a dicing tape.

A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.

In one embodiment, a semiconductor manufacturing apparatus includes a reformed layer former configured to partially reform a first substrate to form a reformed layer between first and second portions in the first substrate, a peeling layer former configured to form a peeling layer between the second portion and a second substrate provided on the first substrate, and a remover configured to remove the second portion from the second substrate while causing the first portion to remain on the second substrate. The remover includes a heater to heat the first or second portion, to peel the second portion from the second substrate at the peeling layer and divide the first and second portions from each other, and a mover to move the second substrate relative to the second portion, to remove the second portion from the second substrate while causing the first portion to remain on the second substrate.

A processing apparatus includes a chuck table, a first and second image capturing units, a display device, and a controller. The first image capturing unit obtains a first image group of images captured of a processed groove in the workpiece at different positions along a thicknesswise direction, each including a piece of first image information representing a shape of the processed groove. The second image capturing unit obtains a second image group of images captured of the processed groove at different positions along the thicknesswise direction of the workpiece, each including a piece of second image information representing a shape of the processed groove. The controller orders the pieces of at least either the first or the second image information into a sequence along the thicknesswise direction, thereby generating a three-dimensional image of the processed groove, and displays the three-dimensional image on the display device.

The present application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method includes: providing a substrate, the substrate including a first semiconductor material layer, a silicon-germanium compound layer and a second semiconductor material layer that are stacked sequentially; forming, in the substrate, first trenches extending along a first direction and second trenches extending along a second direction, and the first trenches and the second trenches separating the substrate into a plurality of spaced pillar structures; doping the pillar structures, such that the silicon-germanium compound layer forms a channel region; and forming a dielectric layer on an outer peripheral surface of each of the pillar structures, and a gate on an outer peripheral surface of the dielectric layer, the gate being opposite to at least a part of the channel region.

Provided is a method for manufacturing a semiconductor structure. It includes: forming first grooves filled with a first dielectric layer and extending in a first direction in a substrate; forming second grooves extending in a second direction in the substrate and the first dielectric layer, the second grooves and the first grooves being intersected and defining discrete active columns in the substrate; depositing second dielectric layers on sidewalls of the second grooves; depositing sacrificial layers in the second grooves, the sacrificial layers being sandwiched between the second dielectric layers; removing part of the first dielectric layer and part of the second dielectric layer, and forming hole structures extending in the second direction, the hole structures surrounding the active columns, and adjacent hole structures being separated by the sacrificial layers; forming word lines in the hole structures; and removing the sacrificial layers to form air gaps between adjacent word lines.

A first conductor pattern is formed on a semiconductor substrate of a scribing region via an insulating film. A plurality of second conductor patterns connected to the first conductor pattern are formed on the first conductor pattern. A third conductor pattern connected to the plurality of second conductor patterns is formed on the plurality of second conductor pattern. The scribing region is cut off in a Y direction by using a dicing blade so that a part of the scribing region is left in a chip region. In an X direction, a width of the dicing blade is narrower than each width of the first and second conductor patterns. After cutting off the scribing region, a part of the first conductor pattern, all or a part of at least one of the plurality of second conductor patterns, and a part of the third conductor pattern are left in the scribing region.

An inspection method for a divided wafer includes a wafer lamination step of stacking a transfer wafer on top of a wafer that has been divided into a plurality of chips, a particle transfer step of, after the wafer lamination step is carried out, positioning the transfer wafer on a lower side and the divided wafer on an upper side and applying a vibration to the wafer stacked on the transfer wafer, to drop particles adhering to side surfaces of the chips onto the transfer wafer, and an inspection step of, after the particle transfer step is carried out, inspecting the particles on the transfer wafer.

A three-dimensional memory device and a method for manufacturing the same are provided. The method includes steps as follows. A semiconductor structure including a substrate and a stacked structure on the substrate is provided. The stacked structure includes alternately stacked gate layers and dielectric layers, or alternately stacked dummy gate layers and dielectric layers. The dummy gate layers are replaceable by the gate layers. A groove is formed in a gate line slit region of the stacked structure. The groove penetrates through the gate layers and multiple layers of the dielectric layers, or through the dummy gate layers and multiple layers of the dielectric layers. An insulating layer is formed on a surface of the stacked structure and in the groove. A depression is formed on a surface of the insulating layer above the groove away from the substrate. The insulating layer is polished to flatten the depression.

A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.