A method for smoothing a surface of a semiconductor portion is disclosed. In the method, an intentional oxide layer is formed on the surface of the semiconductor portion, a treated layer is formed in the semiconductor portion and inwardly of the intentional oxide layer, and then, the intentional oxide layer and the treated layer are removed to obtain a smoothed surface. The method may also be used for widening a recess in a manufacturing process for a semiconductor structure.

The inventive concept provides a substrate treating apparatus. The substrate treating apparatus includes a support unit horizontally maintaining a substrate; a laser irradiation unit for irradiating the substrate with a laser; a photo-detector for detecting an energy of a reflective light reflected from the substrate among a laser irradiated on the substrate; and a processor, and wherein the processor irradiates a first laser of a first output to the substrate, and sets a second output of a second laser for irradiating the substrate to heat the substrate, based on an energy of a first reflective light reflected from the substrate by the first laser detected from the photo-detector.

A method used in forming an array of memory cells comprises forming lines of top-source/drain-region material, bottom-source/drain-region material, and channel-region material vertically there-between in rows in a first direction. The lines are spaced from one another in a second direction. The top-source/drain-region material, bottom-source/drain-region material, and channel-region material have respective opposing sides. The channel-region material on its opposing sides is laterally recessed in the second direction relative to the top-source/drain-region material and the bottom-source/drain-region material on their opposing sides to form a pair of lateral recesses in the opposing sides of the channel-region material in individual of the rows. After the pair of lateral recesses are formed, the lines of the top-source/drain-region material, the channel-region material, and the bottom-source/drain-region material are patterned in the second direction to comprise pillars of individual transistors. Rows of wordlines are formed in the first direction that individually are operatively aside the channel-region material of individual of the pillars in the pairs of lateral recesses and that interconnect the transistors in that individual row. Other embodiments, including structure independent of method, are disclosed.

Methods and apparatuses for selective monitoring of multiple silicon compounds in etchant solutions are provided. Methods can include reacting a test solution comprising a plurality of different silicon compounds with a fluoride-based compound in several conditions to provide different silicon:reagent binding ratios. One of the conditions can include the addition of a co-solvent to the test solution. Concentrations of the multiple silicon compounds can be determined based on the different binding ratios of silicon:reagent. Methods can further include a measuring method such as silicon elemental analysis or measuring of functional groups of a certain silicon form of a first portion of a test solution comprising a plurality of different silicon compounds and reacting a second portion of the solution with a fluoride-based compound to provide a silicon:reagent binding ratio. Concentrations of the multiple silicon compounds can be determined based on the measuring method and binding ratio measurements.

The present invention relates to an etching composition for selectively etching a silicon nitride layer. The etching composition includes an inorganic acid, an epoxy-based silicon compound, and water. The etching composition of the present invention selectively removes a silicon nitride layer while minimizing damage to an underlying metal layer and preventing a silicon oxide layer from being etched.

A method for etching a main surface of a thin layer of a substrate, which comprises immersing the substrate n an etching bath so as to expose the main surface to an etching agent, the substrate being oriented relative to the bath such that: —when it is introduced into the bath, the main surface is gradually immersed from an initial introduction point (PII) to an end introduction point (PFI), at an introduction speed, and —when it exits the bath, the main surface gradually emerges from an initial exit point (PIS) to an end exit point (PFS), at an exit speed, the method being characterized in that: —the introduction speed is chosen in such a way as to etch the main surface according to a first non-uniform profile between the initial introduction point (PII) and the end introduction point (PFI), and/or —the exit speed is chosen in such a way as to etch the main surface according to a second non-uniform profile between the initial exit point (PIS) and the end exit point (PFS), in order to compensate for non-uniformities in the thickness of the thin layer.

A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.

An embodiment comprises: a guide moving in the vertical direction or the horizontal direction; a transfer arm provided on the guide and loading spaced apart wafers; a laser emission unit disposed on the guide and emitting first laser beams at the spaced apart wafers loaded on the transfer arm; and a laser detection unit disposed below the transfer arm and collecting, from among the first laser beams, second laser beams having passed through gaps between the spaced apart wafers.

The present disclosure provides semiconductor devices, fin field-effect transistors and fabrication methods thereof. An exemplary fin field-effect transistor includes a semiconductor substrate; an insulation layer configured for inhibiting a short channel effect and increasing a heat dissipation efficiency of the fin field-effect transistor formed over the semiconductor substrate; at least one fin formed over the insulation layer; a gate structure crossing over at least one fin and covering top and side surfaces of the fin formed over the semiconductor substrate; and a source formed in the fin at one side of the gate structure and a drain formed in the fin at the other side of the gate structure.

A process comprises bonding a semiconductor wafer to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic wafer is transparent. After the bonding, a damage track is formed in the inorganic wafer using a laser that emits the wavelength of light. The damage track in the inorganic wafer is enlarged to form a hole through the inorganic wafer by etching. The hole terminates at an interface between the semiconductor wafer and the inorganic wafer. An article is also provided, comprising a semiconductor wafer bonded to an inorganic wafer. The semiconductor wafer is opaque to a wavelength of light to which the inorganic wafer is transparent. The inorganic wafer has a hole formed through the inorganic wafer. The hole terminates at an interface between the semiconductor wafer and the inorganic wafer.