Fin Field Effect Transistor (FET) (FinFET) complementary metal oxide semiconductor (CMOS) circuits with single and double diffusion breaks for increased performance are disclosed. In one aspect, a FinFET CMOS circuit employing single and double diffusion breaks includes a P-type FinFET that includes a first Fin formed from a semiconductor substrate and corresponding to a P-type diffusion region. The FinFET CMOS circuit includes an N-type FinFET that includes a second Fin formed from the semiconductor substrate and corresponding to an N-type diffusion region. To electrically isolate the P-type FinFET, first and second single diffusion break (SDB) isolation structures are formed in the first Fin on either side of a gate of the P-type FinFET. To electrically isolate the N-type FinFET, first and second double diffusion break (DDB) isolation structures are formed in the second Fin on either side of a gate of the N-type FinFET.

An etcher comprises a bath, a plurality of blades, and a tunnel. The bath includes a first electrode at a first end and a second electrode at a second end. The plurality of blades is configured to fit in the bath. At least one blade of the plurality of blades holds a wafer. At least one tunnel is configured to fit between adjacent blades of the plurality of blades in the bath.

A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration. A middle portion is disposed between the lower portion and upper portion, where the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant. An isolation structure surrounds the fin structure, where a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.

A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

In a substrate processing apparatus, a cup part is moved in an up-down direction to cause a cup exhaust port to selectively overlap a first chamber exhaust port or a second chamber exhaust port. In the state in which the cup exhaust port overlaps the first chamber exhaust port, gas in the cup part is discharged through the cup exhaust port and the first chamber exhaust port by a first exhaust mechanism. In the state in which the cup exhaust port overlaps the second chamber exhaust port, the gas in the cup part is discharged through the cup exhaust port and the second chamber exhaust port by a second exhaust mechanism. In this way, an exhaust mechanism for exhausting gas from the cup part can be easily switched between the first exhaust mechanism and the second exhaust mechanism.

This wet etching method comprises rotating a substrate (W), supplying an etching chemical to a first surface (a surface for forming a device) of the rotating substrate, and supplying an etching inhibitor (DIW) to a second surface (a surface which is not used for forming a device) during the supplying the etching chemical to the substrate. The etching inhibitor moves past an edge (WE) of the substrate to swirl onto the first surface and reaches a first region extending from the edge of the substrate on the periphery of the first surface to a first radial position located radially inward from the edge on the first surface. Thus, it is possible to perform an excellent bevel etching treatment on the upper layer of the substrate having a two-layered film formed thereon.

Systems and methods for automatic sampling of a sample for the determination of chemical element concentrations and control of semiconductor processes are described. A system embodiment includes a remote sampling system configured to collect a sample of phosphoric acid at a first location, the remote sampling system including a remote valve having a holding loop coupled thereto; and an analysis system configured for positioning at a second location remote from the first location, the analysis system coupled to the remote valve via a transfer line, the analysis system including an analysis device configured to determine a concentration of one or more components of the sample of phosphoric acid and including a sample pump at the second location configured to introduce the sample from the holding loop into the transfer line for analysis by the analysis device.

Disclosed are methods of advanced process control (APC) for particular processes. A particular process (e.g., a photolithography or etch process) is performed on a wafer to create a pattern of features. A parameter is measured on a target feature and the value of the parameter is used for APC. However, instead of performing APC based directly on the actual parameter value, APC is performed based on an adjusted parameter value. Specifically, an offset amount (which is previously determined based on an average of a distribution of parameter values across all of the features) is applied to the actual parameter value to acquire an adjusted parameter value, which better represents the majority of features in the pattern. Performing this APC method minimizes dimension variations from pattern to pattern each time the same pattern is generated on another region of the same wafer or on a different wafer using the particular process.

A method of fabricating ultra-thin semiconductor devices includes forming an array of semiconductor dielets mechanically suspended on a frame with at least one tether connecting each semiconductor dielet of the array of semiconductor dielets to the frame.