A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.

A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.

A substrate processing apparatus includes a liquid processing module, including a carry-out/in port of a substrate, in which a first liquid processing device and a second liquid processing device provided at a position farther from the carry-out/in port than the first liquid processing device is are provided; and a transfer device configured to carry the substrate out from and into the liquid processing module. The first liquid processing device performs a first liquid processing on the substrate. The second liquid processing device performs a second liquid processing on the substrate before or after the first liquid processing. The transfer device includes a substrate holder configured to be moved back and forth in a first horizontal direction, and carries the non-processed substrate into the first liquid processing device through the carry-out/in port and carries the processed substrate out from the first liquid processing device through the carry-out/in port.

Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.

A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed.

Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

A process for controlling the heat generated during the manufacture an inhibited hydrofluoric acid aqueous composition comprising: hydrofluoric acid in solution; a weak base; and an alkanolamine;
said process comprising the steps of: providing a pre-determined amount of weak base; adding a pre-determined amount of said hydrofluoric acid to said weak base and obtaining a solution; adding said alkanolamine to the resulting solution of hydrofluoric acid and weak base; mixing until all components are dissolved;
wherein said alkanolamine and hydrofluoric acid are present in a molar ratio of at least 1:1.

The invention relates to compositions and methods for the selective wet etching of a surface of a microelectronic device that contains both silicon nitride (SiN) and polysilicon. An etching composition as described comprises phosphoric acid, certain polysilicon corrosion inhibitors, along with certain silanes. The combination of the two components was found to greatly improve the selectivity of the silicon nitride etching composition in the presence of polysilicon.

Provided is a composition for forming a silica layer, the composition containing a silicon-containing polymer and a solvent, wherein a silica layer formed of the composition for forming the silica layer satisfies Relation 1. The definition of Relation 1 is as described in the specification. The definition of Relation 1 is the same as described in the specification.