Interpenetrating polymer networks (IPNs) for a forming polishing pad for a semiconductor fabrication operation are disclosed. Techniques for forming the polishing pads are provided. In an exemplary embodiment, a polishing pad includes an interpenetrating polymer network formed from a free-radically polymerized material and a cationically polymerized material.

A method for manufacturing a semiconductor structure and the semiconductor structure are provided. In the method, a first wafer is provided, in which the first wafer has a first side and a second side opposite to each other, and a first conductive structure is provided in the first wafer, and an end of the first conductive structure is located in the first wafer. The first wafer is thinned from the second side along a direction perpendicular to the first side, until a thickness of the remaining first wafer reaches a preset thickness to expose the end of the first conductive structure. The thinning includes performing film peeling at least once. In the film peeling, hydrogen ion implantation is performed on the second side to form a hydrogen ion-containing layer in the first wafer; and the first wafer is heated to cause the hydrogen ion-containing layer to fall off.

A CMP slurry composition for polishing a tungsten pattern wafer and a method of polishing a tungsten pattern wafer, the CMP slurry composition includes a solvent; an abrasive agent containing silica modified with a silane compound having at least one nitrogen atom; and an alkylene oxide group-containing fluorine surfactant.

A chemical mechanical polishing apparatus includes a platen to support a polishing pad, a carrier head to hold a substrate against a polishing surface of the polishing pad, a motor to generate relative motion between the platen and the carrier head so as to polish an overlying layer on the substrate, an in-situ vibration monitoring system including a light source to emit a light beam and a sensor that receives a reflection of the light beam from a reflective surface of the polishing pad, and a controller configured to detect exposure of an underlying layer due to the polishing of the substrate based on measurements from the sensor of the in-situ pad vibration monitoring system.

A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.

A wafer polishing head is provided. The wafer polishing head includes a carrier head, a plurality of piezoelectric actuators disposed on the carrier head, and a membrane disposed over the plurality of piezoelectric actuators. The plurality of piezoelectric actuators is configured to provide mechanical forces on the membrane and generate an electrical charge when receiving counterforces of the mechanical forces through the membrane. A wafer polishing system and a method for polishing a substrate using the same are also provided.

The present invention provides Chemical Mechanical Planarization Polishing (CMP) compositions for Shallow Trench Isolation (STI) applications. The CMP compositions contain ceria coated inorganic metal oxide particles as abrasives, such as ceria-coated silica particles; chemical additive selected from the first group of non-ionic organic molecules multi hydroxyl functional groups in the same molecule; chemical additives selected from the second group of aromatic organic molecules with sulfonic acid group or sulfonate salt functional groups and combinations thereof; water soluble solvent; and optionally biocide and pH adjuster; wherein the composition has a pH of 2 to 12, preferably 3 to 10, and more preferably 4 to 9.

Provided herein are polishing pads in which microcapsules that include a polymer material and are dispersed, as well as methods of making and using the same. Such microcapsules are configured to break open (e.g., when the polishing pad is damaged during the dressing process), which releases the polymer material. When contacted with ultraviolet light the polymer material at least partially cures, healing the damage to the polishing pad. Such polishing pads have a longer lifetime and a more stable remove rate when compared to standard polishing pads.

A method of manufacturing a semiconductor device includes performing one or more grinding processes on a backside surface of a device wafer to thin the device wafer from a first thickness to a second thickness. A first chemical mechanical polish (CMP) process is performed on the backside surface of the device wafer to thin the device wafer from the second thickness to a third thickness. A second CMP process is performed on the backside surface of the device wafer to selectively remove device wafer material that is disposed over an active device area of the semiconductor device, where a removal rate of the device wafer material is a function of depth.

A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness T.sub.1 at a first end of the opening, and a thickness T.sub.2 at a second end of the opening, and R.sub.1 is a ratio of T.sub.1 to T.sub.2. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness T.sub.3 at the first end of the opening, a thickness T.sub.4 at the second end of the opening, R.sub.2 is a ratio of T.sub.3 to T.sub.4, and R.sub.1 is greater than R.sub.2.