A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.

A system and method for thinning an integrated circuit (IC) wafer. The system includes a support structure to hold the IC wafer and a mechanism to operate on the IC wafer. The support structure includes one or more inductive coils configured to transmit a power signal to the IC wafer and receive a feedback signal from the IC wafer. The system further includes a process controller to control the operation based at least in part on the feedback signal received from the IC wafer.

Provided is a surface protectant that suppresses corrosion of a semiconductor wafer surface by a basic compound, and reduces defects in the semiconductor wafer. The semiconductor wafer surface protectant of the present invention includes a compound represented by Formula (1) below;
R.sup.1O—(C.sub.3H.sub.6O.sub.2).sub.n—H  (1) where R.sup.1 denotes a hydrogen atom, a hydrocarbon group that has from 1 to 24 carbon atoms and may have a hydroxyl group, or a group represented by R.sup.2CO, where the R.sup.2 denotes a hydrocarbon group having from 1 to 24 carbon atoms; and n indicates an average degree of polymerization of a glycerin unit shown in the parentheses, and is from 2 to 60.

In a chemical mechanical polishing system, a platen shield cleaning assembly is installed on a rotatable platen in a gap between the rotatable platen and a platen shield. The assembly includes a sponge holder attached to the platen and a sponge. The sponge is held by the sponge holder such that an outer surface of the sponge is pressed against an inner surface of the platen shield.

A process for manufacturing a composite structure comprises: a) providing an initial substrate made of monocrystalline silicon carbide, b) epitaxially growing a monocrystalline silicon carbide donor layer on the initial substrate to form a donor substrate 111, c) implanting ions into the donor layer to form a buried brittle plane defining the the donor layer, d) depositing, using liquid injection-chemical vapor deposition at a temperature below 1000° C., a carrier layer on the donor layer, the carrier layer comprising an at least partially amorphous SiC matrix, e) separating the donor substrate along the brittle plane to form an intermediate composite structure comprising the donor layer on the carrier layer f) heat treating the intermediate composite structure at a temperature of between 1000° C. and 1800° C. to crystallize the carrier layer and form the polycrystalline carrier substrate, and g) applying mechanical and/or chemical treatment(s) of the composite structure.

Provided is a wafer polishing method capable of improving nanotopography characteristics within a site on the surface of a wafer having a 2 mm square area or a small area equivalent thereto and a silicon wafer polished by the wafer polishing method, and further provided is a method of chemical-mechanical polishing the surface of a wafer through a polishing step in two or more polishing steps with different polishing rates, in which the in-plane thickness variation (standard deviation) of a polishing pad 150 used in a polishing step with a machining allowance of 0.3 μm or more is 2.0 μm or less.

A chemical mechanical planarization system includes a chemical mechanical planarization pad that rotates during a chemical mechanical planarization process. A chemical mechanical planarization head places a semiconductor wafer in contact with the chemical mechanical planarization pad during the process. A slurry supply system supplies a slurry onto the pad during the process. A pad conditioner conditions the pad during the process. An impurity removal system removes debris and impurities from the slurry.

Methods and apparatuses for dispensing polishing fluids onto a polishing pad within a chemical mechanical polishing (CMP) system are disclosed herein. In particular, embodiments herein relate to a CMP polishing method including urging a substrate against a surface of a pad of a polishing system using a carrier assembly. A fluid is dispensed onto the pad from a fluid delivery assembly at a variable flow rate and a first flow rate of the variable flow rate is pulsed at a frequency and a duty cycle. The frequency refers to a number of pulses of the fluid at the first flow rate per rotation of the pad. The term duty cycle refers to a percentage of the pad exposed to fluid per rotation of the pad. The carrier assembly is translated across a surface of the pad while rotating the carrier assembly about a rotational axis.

According to one embodiment, a polishing apparatus includes a holder for holding a polishing pad for polishing a surface of a substrate. A plurality of pressing members are configured to press a back surface side of the polishing pad while held by the holder. A driving unit is configured to selectively move pressing members in a direction towards the surface of the substrate so as to press the back surface side of the polishing pad.

The present disclosure provides a method for manufacturing vertical device. The method includes: forming a plurality of first grooves in the front side of the N-type heavily doped layer; forming an N-type lightly doped layer in the plurality of first grooves and on the front side of the N-type heavily doped layer; forming second grooves in the N-type lightly doped layer; forming a P-type semiconductor layer in the second grooves and on the front side of the N-type lightly doped layer; planarizing the P-type semiconductor layer; forming a passivation layer on the planarized structure; forming a third groove in the passivation layer, wherein the third groove has a depth equal to a thickness of the passivation layer; and forming a first electrode and a second electrode.