H01L21/30625

Semiconductor device and method

In an embodiment, a method includes: forming a first recess and a second recess in a substrate; growing a first epitaxial material stack in the first recess, the first epitaxial material stack including alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; growing a second epitaxial material stack in the second recess, the second epitaxial material stack including alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped; patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.

Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures

Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

Substrate processing apparatus

A substrate processing apparatus includes a polishing member having a polishing surface configured to perform a polishing of a main surface of a substrate; a first dressing member having a first dressing surface configured to perform a dressing of the polishing surface; a second dressing member having a second dressing surface configured to perform a dressing of the first dressing surface; a holding member configured to hold the polishing member and the second dressing member; and a driving unit configured to, by moving the holding member, switch a first state in which the first dressing surface and the polishing surface come into contact with each other to perform the dressing of the polishing surface and a second state in which the first dressing surface and the second dressing surface come into contact with each other to perform the dressing of the first dressing surface.

Gate-all-around integrated circuit structures having vertically discrete source or drain structures

Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

CHEMICAL MECHANICAL POLISHING COMPOSITION AND CHEMICAL MECHANICAL POLISHING METHOD

Provided are a chemical mechanical polishing composition and a chemical mechanical polishing method that can polish a semiconductor substrate containing an electric conductor metal, such as tungsten or cobalt, flat and at high speed, and reduce post-polishing surface defects. The chemical mechanical polishing composition contains (A) silica particles having the functional group represented by general formula (1), and (B) at least one selected from the group consisting of a carboxylic acid having an unsaturated bond and a salt thereof. (1): —COO-M+ (M+ represents a monovalent cation.)

Polishing composition, manufacturing method of polishing composition, polishing method, and manufacturing method of semiconductor substrate

The present invention provides, in polishing an object to be polished that contains an (a) material having silicon-nitrogen bonding and (b) other materials, means that is capable of improving a ratio of a polishing speed of the (a) material to a polishing speed of the (b) materials. The present invention relates to a polishing composition used for polishing an object to be polished that contains an (a) material having silicon-nitrogen bonding and (b) other materials, the polishing composition containing: organic acid-immobilized silica; a dispersing medium; a selection ratio improver that improves a ratio of a polishing speed of the (a) material to a polishing speed of the (b) materials; and an acid, in which the selection ratio improver is organopolysiloxane having a hydrophilic group.

Semiconductor device
11521917 · 2022-12-06 · ·

A semiconductor device includes a chip that includes a mounting surface, a non-mounting surface, and a side wall connecting the mounting surface and the non-mounting surface and has an eaves portion protruding further outward than the mounting surface at the side wall and a metal layer that covers the mounting surface.

Method for fabricating a semiconductor device
11521892 · 2022-12-06 · ·

The present application discloses a method for fabricating a semiconductor device with liners. The method includes providing a substrate having a first surface and a second surface opposite to the first surface, inwardly forming a trench on the first surface of the substrate, forming a plurality of liners positioned on side surfaces of the trench, forming a first insulating segment filling the trench, and removing part of the substrate from the second surface to expose the first insulating segment and the plurality of liners.

ASYMMETRY CORRECTION VIA VARIABLE RELATIVE VELOCITY OF A WAFER

Certain aspects of the present disclosure provide techniques for a method of removing material on a substrate. An exemplary method includes rotating a substrate about a first axis in a first direction and urging a surface of the substrate against a polishing surface of a polishing pad while rotating the substrate, wherein rotating the substrate about the first axis includes rotating the substrate a first angle at a first rotation rate, and then rotating the substrate a second angle at a second rotation rate, and the first rotation rate is different from the second rotation rate.

CHEMICAL-MECHANICAL POLISHING COMPOSITION, RINSE COMPOSITION, CHEMICAL-MECHANICAL POLISHING METHOD, AND RINSING METHOD

Provided is a chemical-mechanical polishing composition comprising an abrasive, a basic component, at least one compound selected from the group consisting of a quaternary polyammonium salt, a quaternary ammonium salt having 6 or more carbon atoms, and an alkylated polymer having an amide structure, and an aqueous carrier; a rinse composition comprising the at least one compound and an aqueous carrier, as well as a method of chemically-mechanically polishing a substrate, and a method of rinsing a substrate, in which the respective compositions are used.