A thin film transistor, its manufacturing method, and a display device are provided. The method comprises: forming a gate metal layer (35), forming a step-like gate structure (352) by one patterning process; performing a first ion implantation procedure to forming a first heavily doped area (39a) and a second heavily doped area (39b), the first heavily doped area (39a) being separated apart from the second heavily doped area (39b) by a first length; forming a gate electrode (353) from the step-like gate structure (352); performing a second ion implantation procedure to form a first lightly doped area (38a) and a second lightly doped area (38b), the first lightly doped area (38a) being separated apart from the second lightly doped area (38b) by a second length less than the first length. By the above method, the process for manufacturing the LTPS TFT having the lightly doped source/drain structure can be simplified.

An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.

Forming a semiconductor arrangement includes non-destructively determining a first spacer height of a first sidewall spacer adjacent a dummy gate and a second spacer height of a second sidewall spacer adjacent the dummy gate based upon a height of a photoresist as measured using optical critical dimension (OCD) spectroscopy. When the photoresist is sufficiently uniform, a hard mask etch is performed to remove a hard mask from the dummy gate and to remove portions of sidewall spacers of the dummy gate. A gate electrode is formed between the first sidewall spacer and the second sidewall spacer to form a substantially uniform gate. Controlling gate formation based upon photoresist height as measured by OCD spectroscopy provides a non-destructive manner of promoting uniformity.

Disclosed is a method for manufacturing a semiconductor device, including a step of yielding a pattern 2a of a polysiloxane-containing composition over a substrate 1, and a step of forming an ion impurity region 6 in the substrate, wherein, after the step of forming an ion impurity region, the method further includes a step of firing the pattern at a temperature of 300 to 1,500° C. This method makes it possible that after the formation of the ion impurity region in the semiconductor substrate, the pattern 2a of the polysiloxane-containing composition is easily removed without leaving any residual. Thus, the yield in the production of a semiconductor device can be improved and the tact time can be shortened.

Provided is a polishing composition which is capable of sufficiently suppressing a polishing speed for a low relative permittivity material.

Disclosed is a polishing composition to be used for polishing a material having a relative permittivity of 4 or less, the polishing composition including abrasive grains and an organic compound, the organic compound having a polyoxyalkylene group and an aliphatic hydrocarbon group containing three or more carbon atoms.

A fan-out wafer-level-process integrated circuit is provided in which a plurality of interconnects couple to pads on an encapsulated die. The interconnects have a pad-facing surface that couples to a corresponding pad through a seed layer. The seed layer does not cover the sidewalls of the interconnects.

An integrated circuit device includes spaced apart conductive patterns on a substrate surface, and a supporting pattern on the substrate surface between adjacent ones of the conductive patterns and separated therefrom by respective gap regions. The adjacent ones of the conductive patterns extend away from the substrate surface beyond a surface of the supporting pattern therebetween. A capping layer is provided on respective surfaces of the conductive patterns and the surface of the supporting pattern. Related fabrication methods are also discussed.

A display panel and manufacturing method. The method includes: forming a source electrode, a drain electrode and a channel on a substrate; depositing a first insulation layer; forming multiple color photoresists on the first insulation layer, and the source electrode, the drain electrode and the channel are located between two adjacent color photoresists; forming a gate electrode and a common electrode by a same process, and the gate electrode is located on the first insulation layer, and the common electrode is located on the photoresist; forming a second insulation layer having a through hole communicated with the source electrode on the gate electrode and the common electrode; forming a pixel electrode on the second insulation layer. The pixel electrode contacts with the source electrode through the through hole, and a storage capacitor is formed. The storage capacitor can be increased and the current leakage of the pixel electrode improved.

Disclosed is a pattern forming method including: forming an acrylic resin layer on an underlayer; forming an intermediate layer on the acrylic resin layer; forming a patterned EUV resist layer on the intermediate layer; forming a pattern on the acrylic resin layer by etching the intermediate layer and the acrylic resin layer with the EUV resist layer as an etching mask; removing the EUV resist layer and the intermediate layer after the pattern is formed on the acrylic resin layer; and smoothing a surface of the acrylic resin layer after the EUV resist layer and the intermediate layer are removed.

A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.