A semiconductor device includes: a first semiconductor structure; a second semiconductor structure on the first semiconductor structure; an active region between the first semiconductor structure and the second semiconductor structure, wherein the active region includes multiple alternating well layers and barrier layers, wherein each of the barrier layers has a band gap, the active region further includes an upper surface facing the second semiconductor structure and a bottom surface opposite the upper surface; an electron blocking region between the second semiconductor structure and the active region, wherein the electron blocking region includes a band gap, and the band gap of the electron blocking region is greater than the band gap of one of the barrier layers; a first aluminum-containing layer between the electron blocking region and the active region, wherein the first aluminum-containing layer has a band gap greater than the band gap of the electron blocking region; a confinement layer between the first aluminum-containing layer and the active region, wherein the confinement layer includes a thickness smaller than the thickness of one of the barrier layers; and a p-type dopant above the bottom surface of the active region and comprising a concentration profile comprising a peak shape having a peak concentration value, wherein the peak concentration value lies in the electron blocking region.

A low-resistance thick-wire integrated inductor may be formed in an integrated circuit (IC) device. The integrated inductor may include an elongated inductor wire defined by a metal layer stack including an upper metal layer, middle metal layer, and lower metal layer. The lower metal layer may be formed in a top copper interconnect layer, the upper metal layer may be formed in an aluminum bond pad layer, and the middle metal layer may comprise a copper tub region formed between the aluminum upper layer and copper lower layer. The wide copper region defining the middle layer of the metal layer stack may be formed concurrently with copper vias of interconnect structures in the IC device, e.g., by filling respective openings using copper electrochemical plating or other bottom-up fill process. The elongated inductor wire may be shaped in a spiral or other symmetrical or non-symmetrical shape.

A method of manufacturing a semiconductor device is provided. The method includes forming a preliminary via structure through a portion of a substrate; partially removing the substrate to expose a portion of the preliminary via structure; forming a protection layer structure on the substrate to cover the portion of the preliminary via structure that is exposed; partially etching the protection layer structure to form a protection layer pattern structure and to partially expose the preliminary via structure; wet etching the preliminary via structure to form a via structure; and forming a pad structure on the via structure to have a flat top surface.

A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.

A semiconductor device includes a substrate; multi-level interconnections disposed on the substrate; a first passivation layer containing hydrogen and covering top interconnections among the multi-level interconnections; a second passivation layer disposed over the first passivation layer to prevent out-diffusion of the hydrogen from the first passivation layer; an in-line top dielectric layer over the second passivation layer; an in-line redistribution layer connected to one among the top interconnections by passing through the in-line top dielectric layer, the second passivation layer, and the first passivation layer; and a hydrogen blocking liner disposed between the in-line redistribution layer and the first passivation layer.

An embodiment is a method including forming a first passive device in a first wafer, forming a first dielectric layer over a first side of the first wafer, forming a first plurality of bond pads in the first dielectric layer, planarizing the first dielectric layer and the first plurality of bond pads to level top surfaces of the first dielectric layer and the first plurality of bond pads with each other, hybrid bonding a first device die to the first dielectric layer and at least some of the first plurality of bond pads, and encapsulating the first device die in a first encapsulant.

An electronic subassembly encompassing at least one carrier substrate, an electronic circuit being embodied on at least one carrier substrate surface. The electronic subassembly encompasses at least one mechanical connecting boss that is connected, in a substrate connection region, to at least one of the carrier substrate surfaces. The connecting boss, conversely, has, on a side facing away from the substrate connection region, a terminating boundary layer which is made of a metal oxide and which is embodied to furnish an adhesive bonding surface for an adhesive layer in order to constitute an adhesively bonded composite assemblage with a join participant.

A memory device includes a memory array, disposed on a substrate of a peripheral-circuit structure; a conductive plug, extending through the memory array and connected to the peripheral-circuit structure; and a conductive pad layer, disposed over the memory array and including a plurality of conductive pads spaced apart from each other. The conductive plug protrudes into a corresponding conductive pad of the plurality of conductive pads.

To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.

The disclosed technology generally relates to forming a titanium nitride-based thin films, and more particularly to a conformal and smooth titanium nitride-based thin films and methods of forming the same. In one aspect, a method of forming a thin film comprising one or both of TiSiN or TiAlN comprises exposing a semiconductor substrate to one or more vapor deposition cycles at a pressure in a reaction chamber greater than 1 torr, wherein a plurality of the vapor deposition cycles comprises an exposure to a titanium (Ti) precursor, an exposure to a nitrogen (N) precursor and an exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.