A semiconductor package includes a frame having a through hole, an electronic component disposed in the through hole, a metal layer disposed on either one or both of an inner surface of the frame and an upper surface of the electronic component, a redistribution portion disposed below the frame and the electronic component, and a conductive layer connected to the metal layer.

An integrated circuit device has a substrate including a dielectric layer patterned with a pattern which includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed on the set of features in the patterned dielectric. A ruthenium layer is disposed on the adhesion promoting layer. A cobalt layer is disposed on the ruthenium layer filling a first portion of the set of features. The cobalt layer has a u-shaped cross section having a thicker bottom layer than side layers. The cobalt layer is formed using a physical vapor deposition process. A metal layer is disposed on the cobalt layer filling a second, remainder portion of the set of features.

A power module includes a first terminal, a second terminal, and a number of semiconductor die coupled between the first terminal and the second terminal. The semiconductor die are configured to provide a low-resistance path for current flow from the first terminal to the second terminal during a forward conduction mode of operation and a high-resistance path for current flow from the first terminal to the second terminal during a forward blocking configuration. Due to improvements made to the power module, it is able to pass a temperature, humidity, and bias test at 80% of its rated voltage for at least 1000 hours.

A pattern is provided in a dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. The set of features have a first dimension. An adhesion promoting layer disposed over the patterned dielectric is deposited. A ruthenium layer disposed over the adhesion promoting layer is deposited. A cobalt layer is deposited over the ruthenium layer. A high temperature thermal anneal is performed which creates a ruthenium cobalt alloy layer to cover surfaces of the set of features. A metal layer is deposited disposed over the ruthenium cobalt alloy layer to form a set of metal conductor structures. In another aspect of the invention, a device is created using the method.

An integrated circuit device includes a substrate including a patterned dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed over the set of features in the patterned dielectric. A ruthenium cobalt alloy layer is disposed over the adhesion promoting layer. A metal layer is disposed over the ruthenium cobalt alloy layer filling the set of features.

Use of a single alloy conductor to form simultaneous ohmic contacts (SOC) to n- and p-type 4H-SiC. The single alloy conductor also is an effective diffusion barrier against gold (AU) and oxygen (O.sub.2) at high temperatures (e.g., up to 800 C.). The innovation may also provide an effective interconnecting metallization in a multi-level metallization device scheme.

A power module includes a first terminal, a second terminal, and a number of semiconductor die coupled between the first terminal and the second terminal. The semiconductor die are configured to provide a low-resistance path for current flow from the first terminal to the second terminal during a forward conduction mode of operation and a high-resistance path for current flow from the first terminal to the second terminal during a forward blocking configuration. Due to improvements made to the power module, it is able to pass a temperature, humidity, and bias test at 80% of its rated voltage for at least 1000 hours.

An integrated circuit substrate and its method of production are described. The integrated circuit substrate comprises at least an internal conductive trace layer formed by one or more internal conductive traces that is deposited on a partially or completely removable carrier; and a dielectric layer encapsulating the internal conductive trace layer through a lamination process or a printing process. The top surface of the topmost internal conductive trace layer and bottom surface of the bottommost internal conductive trace layer are exposed and not covered by the dielectric layer. External conductive trace layer can also be deposited outside of the dielectric layer. The internal conductive trace layers are deposited through plating or printing of an electronically conductive material, whereas the external conductive trace layer is deposited through electroless and electroplating, or printing of the electronically conductive layer.

Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver-containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

An object of the present invention is to stabilize and strengthen the strength of a bonding part between a metal electrode on a semiconductor chip and metal wiring connected thereto using a simple structure. Provided is a semiconductor device including a metal layer 130 on a surface of a metal electrode 120 formed on a semiconductor chip 110, the metal layer 130 consisting of a metal or an alloy different from a constituent metal of the metal electrode 120, metal wiring 140 is connected to the metal layer 130 via a bonding part 150, wherein the constituent metal of the metal layer 130 is a metal or an alloy different from the constituent metal of the metal electrode 120, and the bonding part 150 has an alloy region harder than the metal wiring 140.