Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer.

A semiconductor structure and the manufacturing method thereof are disclosed. An exemplary method includes receiving a workpiece including a dielectric layer and a contact via extending through the dielectric layer, selectively forming a metal feature on a top surface of the contact via, forming a barrier layer over the metal feature and the dielectric layer, wherein the contact via is spaced apart from the barrier layer, and, forming a metal fill layer over the barrier layer. The metal feature is formed of a first material and the barrier layer is formed of a second material different from the first material.

Conductive lines, integrated chips, and methods of forming the same include forming a first metal liner in a trench in a substrate. The trench is filled with a second metal. The second metal is overpolished with a chemical mechanical planarization (CMP) process that stops on the first metal liner, such that the second metal is reduced to a level that is below a height of a top surface of the substrate. The trench is filled with a third metal.

A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers.

Methods of depositing a metal film with high purity are discussed. A catalyst enhanced CVD process is utilized comprising an alkyl halide catalyst soak and a precursor exposure. The precursor comprises a metal precursor having the general formula (I): M-L.sub.1(L.sub.2).sub.y, wherein M is a metal, L.sub.1 is an aromatic ligand, L.sub.2 is an aliphatic ligand, and y is a number in the range of from 2 to 8 to form a metal film on the substrate surface, wherein the L.sub.2 comprises 1,5-hexdiene, 1,4-hexadiene, and less than 5% of 1,3-hexadiene. Selective deposition of a metal film with high purity on a metal surface over a dielectric surface is described.

A method for forming a semiconductor structure is provided. The method includes depositing a hard mask layer over a substrate. The method further includes depositing a silver precursor layer over the hard mask layer. The method further includes exposing portions of the silver precursor layer to a radiation, the radiation causing a reduction of silver ions in the irradiated portions of the silver precursor layer. The method further includes removing non-irradiated portions of the silver precursor layer, resulting in a plurality of silver seed structures.

A semiconductor structure includes a substrate, a plurality of conductive features disposed over the substrate, and an isolation structure between conductive features and separating the conductive features from each other. Each of the conductive features includes a first metal layer and a 2D material layer. Another semiconductor structure includes a first conductive feature, a dielectric structure over the first conductive feature, a second conductive feature in the dielectric structure and coupled to the first conductive feature, and a conductive line over and coupled to the second conductive feature. In some embodiments, the conductive line includes a first 3D material layer, a first 2D material layer, and a second 3D material layer. The first 2D material layer is disposed between the first 3D material layer and the second 3D material layer.

A structure may include an interconnect-level dielectric layer containing a dielectric material and overlying a substrate, and a metal interconnect structure embedded in the interconnect-level dielectric layer and including a graded metallic alloy layer and a metallic fill material portion. The graded metallic alloy layer includes a graded metallic alloy of a first metallic material and a second metallic material. The atomic concentration of the second metallic material increases with a distance from an interface between the graded metallic alloy and the interconnect-level dielectric layer. The graded metallic alloy layer may be formed by simultaneous or cyclical deposition of the first metallic material and the second metallic material. The first metallic material may provide barrier property, and the second metallic material may provide adhesion property.

Embodiments of the disclosure provide methods which reduce or eliminate lateral growth of a selective tungsten layer. Further embodiments provide an integrated clean and deposition method which improves the selectivity of selectively deposited tungsten on trench structures. Additional embodiments provide methods for forming a more uniform and selective bottom-up gap fill for trench structures with improved film properties.

An integrated circuit structure includes a first layer comprising silicon and at least one of carbon, oxygen, or hydrogen, and a device layer including a plurality of transistors above the first layer. A first interconnect structure is above the device layer and includes first conductive interconnect features. A second interconnect structure is below the first layer and includes second conductive interconnect features. In an example, one or more of the second conductive interconnect features pass through a bottom surface of the first layer. One or more third conductive interconnect features vertically extend through the device layer to a top surface of the first layer. In an example, the one or more third conductive interconnect features are in contact with the corresponding one or more of the second conductive interconnect features that pass through the bottom surface of the first layer.