The present disclosure relates to method for preparing a semiconductor device with a composite landing pad. The method includes forming a first dielectric layer over a semiconductor substrate. The semiconductor device also includes forming a lower metal plug and a barrier layer in the first dielectric layer. The lower metal plug is surrounded by the barrier layer. The semiconductor device further includes forming an inner silicide portion over the lower metal plug, and an outer silicide portion over the barrier layer. A topmost surface of the outer silicide portion is higher than a topmost surface of the inner silicide portion.

A method of forming a titanium nitride film includes: forming the titanium nitride film by alternately repeating supplying a raw material gas, which contains a titanium compound including chlorine and titanium, to a substrate accommodated in a processing container, and supplying a reaction gas, which contains a nitrogen compound including nitrogen and reacts with the titanium compound to form titanium nitride, to the substrate, wherein the forming the titanium nitride film is executed under a condition in which a pressure in the processing container is set within a range of 2.7 kPa to 12.6 kPa so that a specific resistance of the titanium nitride film becomes 57 micro-ohm-cm or less.

A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes source/drain structures on opposite sides of the gate structure. The semiconductor structure also includes a dielectric layer over the gate structure and the source/drain structures. The semiconductor structure also includes a via plug passing through the dielectric layer and including a first group IV element. The dielectric layer includes a second group IV element, a first compound, and a second compound, and the second compound includes elements in the first compound and the first group IV element.

Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.

The present disclosure describes semiconductor devices and methods for forming the same. A method for forming a semiconductor device includes forming a source/drain structure and forming a gate structure. The method also includes performing a cleaning process on the source/drain structure and the gate structure. The method also includes disposing a portion of a byproduct of the cleaning process on a top surface of the gate structure and etching the portion of the byproduct so a remaining portion of the byproduct is formed on the top surface of the gate structure. The method further includes forming a gate contact structure, including depositing a metal material on the remaining portion of the byproduct to form a compound containing the metal material and the remaining portion of the byproduct. The method also includes forming a barrier layer between the compound and the top surface of the gate structure.

A method for fabricating an advanced metal conductor structure is described. A pattern in a dielectric layer is provided. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is created over the patterned dielectric. A ruthenium layer is deposited over the adhesion promoting layer. Using a physical vapor deposition process, a cobalt layer is deposited over the ruthenium layer. A thermal anneal is performed which reflows the cobalt layer to fill the set of features to form a set of metal conductor structures. In another aspect of the invention, an integrated circuit device is formed using the method.

High-voltage semiconductor devices are provided. The high-voltage semiconductor device includes a substrate and an isolation structure in the substrate. The high-voltage semiconductor device includes a gate structure disposed on the substrate, wherein the gate structure is separated from the isolation structure by a distance. The high-voltage semiconductor device also includes a metal electrode disposed on the gate structure, wherein the metal electrode extends to directly above the isolation structure. The high-voltage semiconductor device further includes an interconnection structure including the lowest metal layer, wherein the metal electrode is between the lowest metal layer and the gate structure. Methods of manufacturing the high-voltage semiconductor device are also provided.

A semiconductor structure and a method of fabricating the same is disclosed. The semiconductor device includes a conductive structure that comprises: an upper conductive line arranged above and in electrical connection with a circuit component in a lower device layer through a via plug, wherein the upper conductive line extends laterally over the via plug; an interposing layer having a substantially uniform thickness arranged between the via plug and the upper conductive line, and extending laterally beyond a planar projection of the via plug, wherein the upper conductive line is in electrical connection with the via plug through the interposing layer; and an overlayer is disposed over the upper conductive line.

Some embodiments include an integrated assembly having a first graphene-containing-material offset from a second graphene-containing-material. The first graphene-containing-material includes a first graphene-layer-stack with first metal interspersed therein. The second graphene-containing-material includes a second graphene-layer-stack with second metal interspersed therein. A conductive interconnect couples the first and second graphene-containing materials to one another.

A semiconductor structure and the method of forming the same are provided. The method of forming a semiconductor structure includes forming a recess feature in a basal layer, forming a metal layer on the basal layer, exposing the metal layer to a tungsten halide gas to form an oxygen-deficient metal layer, and forming a bulk tungsten layer on the oxygen-deficient metal layer.