A first conductive feature has a dielectric layer formed thereover. An opening is formed in the dielectric layer to expose a portion of the first conductive feature. A first barrier layer is formed over the first conductive feature and over a top surface of the dielectric layer. A second barrier layer is formed over the first barrier layer and on sidewalls of the opening. The second barrier layer is removed, resulting in at least a portion of the first barrier layer disposed over the first conductive feature. A second conductive feature is formed over the portion of the first barrier layer. Sidewalls of the second conductive feature directly contact the dielectric layer.

Provided are a method of manufacturing a semiconductor package substrate, a semiconductor package substrate manufactured using the method of manufacturing a semiconductor package substrate, a method of manufacturing a semiconductor package, and a semiconductor package manufactured using the method of manufacturing a semiconductor package. The method of manufacturing a semiconductor package substrate includes forming first grooves or first trenches in a bottom surface of a base substrate having a top surface and the bottom surface and formed of a conductive material; filling the first grooves or trenches with resin; curing the resin; removing exposed portions of the resin overfilled in the first grooves or trenches; etching the top surface of the base substrate to expose at least portions of the resin filled in the first grooves or trenches; and forming a second groove or a second trench in the bottom surface of the base substrate.

A method of forming an electrode on a substrate is disclosed. The method may include: contacting the substrate with a first vapor phase reactant comprising a titanium tetraiodide (TiI.sub.4) precursor; contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor; and depositing a titanium nitride layer over a surface of the substrate thereby forming the electrode; wherein the titanium nitride layer has an electrical resistivity of less than 400 -cm. Related semiconductor device structures including a titanium nitride electrode deposited by the methods of the disclosure are also provided.

An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

A method of making a GaN device includes: forming a GaN substrate; forming a plurality of spaced-apart first metal contacts directly on the GaN substrate; forming a layer of insulating GaN on the exposed portions of the upper surface; forming a stressor layer on the contacts and the layer of insulating GaN; forming a handle substrate on the first surface of the stressor layer; spalling the GaN substrate that is located beneath the stressor layer to separate a layer of GaN and removing the handle substrate; bonding the stressor layer to a thermally conductive substrate; forming a plurality of vertical channels through the GaN to define a plurality of device structures; removing the exposed portions of the layer of insulating GaN to electrically isolate the device structures; forming an ohmic contact layer on the second surface; and forming second metal contacts on the ohmic contact layer.

A semiconductor device includes a first lower plug and a second lower plug disposed over a semiconductor substrate. The semiconductor device also includes a first landing pad disposed over a top surface and upper sidewalls of the first lower plug, and a first upper plug disposed over the first landing pad and electrically connected to the first lower plug. A width of the first lower plug is greater than a width of the first upper plug. The semiconductor device further includes a dielectric layer disposed over the semiconductor substrate. The first lower plug, the second lower plug, the first landing pad and the first upper plug are disposed in the dielectric layer, and the dielectric layer includes an air gap disposed between the first lower plug and the second lower plug.

A semiconductor structure is provided. The semiconductor structure includes a gate structure over a fin structure. The semiconductor structure also includes a source/drain structure in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a first contact plug over the source/drain structure. The semiconductor structure also includes a first via plug over the first contact plug. The semiconductor structure also includes a dielectric layer surrounding the first via plug. The first via plug includes a first group IV element and the dielectric layer includes the first group IV element and a second group IV element.

An integrated circuit for a flash memory device with enlarged spacing between select and memory gate structures is provided. The enlarged spacing is obtained by forming corner recesses at the select gate structure so that a top surface with a reduced dimension of the select gate structure is obtained. In one example, a semiconductor substrate having memory cell devices formed thereon, the memory cell devices include a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a plurality of select gate structures and a plurality of memory gate structures formed adjacent to the plurality of select gate structures, wherein at least one of the plurality of select gate structures have a corner recess formed below a top surface of the at least one of the plurality of select gate structures.

Semiconductor device packages include a redistribution layer (RDL) with carbon-based conductive elements. The carbon-based material of the RDL may have low electrical resistivity and may be thin (e.g., less than about 0.2 m). Adjacent passivation material may also be thin (e.g., less than about 0.2 m). Methods for forming the semiconductor device packages include forming the carbon-based material (e.g., at high temperatures (e.g., at least about 550 C.)) on an initial support wafer with a sacrificial substrate. Later or separately, components of a device region of the package may be formed and then joined to the initial support wafer before the sacrificial substrate is removed to leave the carbon-based material joined to the device region.

A method of forming an electrode on a substrate is disclosed. The method may include: contacting the substrate with a first vapor phase reactant comprising a titanium tetraiodide (TiI.sub.4) precursor; contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor; and depositing a titanium nitride layer over a surface of the substrate thereby forming the electrode; wherein the titanium nitride layer has an electrical resistivity of less than 400 -cm. Related semiconductor device structures including a titanium nitride electrode deposited by the methods of the disclosure are also provided.