A semiconductor device includes a semiconductor substrate having a predetermined region in which a standard cell is disposed, and also includes: a first circuit connected to a first ground power line; a second circuit that is connected to a second ground power line and formed from the standard cells; and a protection circuit interposed and connected between the first circuit and the second circuit. The protection circuit includes: a resistor connected in series between the first circuit and the second circuit; and a protector that is interposed and connected between a node of the resistor on the second circuit side and the second ground power line and clamps a potential difference between the node and the second ground power line to a predetermined voltage or lower. The protection circuit is formed in a protection cell disposed in the predetermined region.

An electrostatic discharge circuit is provided. The electrostatic discharge circuit includes a cascade transistor configuration and a control circuit. The cascade transistor configuration includes a first transistor and a second transistor coupled between a power supply node and a ground node. The control circuit is coupled to the cascade transistor configuration, and coupled between the power supply node and the ground node. The control circuit includes a voltage drop circuit coupled to the power supply node and the first transistor, and an electrostatic discharge detecting circuit between the voltage drop circuit and the ground node. The electrostatic discharge detecting circuit is coupled to the first transistor and the second transistor.

An electrostatic protection structure able to discharge static electricity of either polarity from a functional circuit including signal lines includes a discharge electrode and a plurality of electrostatic protection units electrically coupled to the discharge electrode. Each electrostatic protection unit includes a first TFT and a second TFT. The first TFT includes first gate, source, and drain, the second TFT includes second gate, source, and drain. The first gate and the first drain are electrically connected to one signal line. The first source is electrically connected to the second drain, the first drain is electrically connected to the second source, the second gate is electrically connected to the discharge electrode, and the second gate is electrically connected to the second drain.

A method of manufacturing a mask may include identifying an error pattern of final patterns formed on a substrate, correcting a first target pattern on the basis of the error pattern, fracturing a first mask layout into a plurality of first segments on the basis of the corrected first target pattern, and correcting the first mask layout by biasing a plurality of first target segments corresponding to a first final target among the plurality of segments. The first mask layout may include a first extension pattern, final targets disposed in zigzags, and the first final target corresponding to the error pattern, and each of the plurality of first segments may corresponds to one of the final targets.

An integrated circuit includes an input/output (I/O) pad, an electrostatic discharge (ESD) primary circuit and a bias voltage generator. The electrostatic discharge primary circuit includes a first transistor. A first terminal of the first transistor is coupled to the I/O pad. The bias voltage generator is configured to provide a gate bias signal to the gate terminal of the first transistor. The bias voltage generator provides the gate bias signal at a first voltage level in response to that an ESD event occurs on the I/O pad. The bias voltage generator provides the gate bias signal at a second voltage level in response to that no ESD event occurs on the I/O pad. The first voltage level is lower than the second voltage level.

An electro-static discharge (ESD) protection circuit utilizes a gate-drain breakdown characteristic of high electron mobility transistors (HEMTs) in a dual stacked configuration to provide a discharge path for electro-static discharges, while having a minimal effect on the associated circuit which is being protected.

When an ESD element is operated, for the purpose of suppressing heat generation and causing uniform current to flow through all channels of all transistors included in the ESD element, various substrate potentials existing in the transistors and the channels of a multi finger type ESD element are electrically connected via a low resistance substrate, and further, are set to a potential that is different from a Vss potential. In this manner, the current is uniformized and heat generation is suppressed through low voltage operation to improve an ESD tolerance.

The present disclosure relates to a semiconductor device. The semiconductor device includes a substrate, a first doping region, a second doping region, a third doping region, a first transient block unit and a second transient block unit. The first doping region is in the substrate. The second doping region is in the first doping region. The third doping region is in the first doping region. The first transient block unit is electrically connected to the second doping region. The second transient block unit is electrically connected between the third doping region and the first transient block unit.

A semiconductor integrated circuit device may include a pad, a first voltage protection circuit and a second voltage protection circuit. The first voltage protection circuit may be connected with the pad. The second voltage protecting circuit may be connected between the first voltage protection circuit and a ground terminal. The first voltage protection circuit may include a gate positive p-channel metal oxide semiconductor (GPPMOS) transistor. The second voltage protection circuit may include serially connected GPPMOS transistors.

An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.