When an ESD element is operated, for the purpose of suppressing heat generation and causing uniform current to flow through all channels of all transistors included in the ESD element, various substrate potentials existing in the transistors and the channels of a multi finger type ESD element are electrically connected via a low resistance substrate, and further, are set to a potential that is different from a Vss potential. In this manner, the current is uniformized and heat generation is suppressed through low voltage operation to improve an ESD tolerance.

Aspects of the invention provide a compact semiconductor device having a surge protection element, which can reliably protect against surge and is unlikely to be affected by manufacturing variation. By forming a parasitic n-p-n transistor on a guard ring, and adopting the parasitic n-p-n transistor as a surge protection element, it is possible to provide a compact semiconductor device having a surge protection element. Also, by adopting the parasitic n-p-n transistor as a surge protection element, it is possible to reduce the operating resistance in comparison with when using a parasitic n-p-n transistor as a surge protection element, and thus possible to improve the surge protection function. Further, by providing one surge protection element on the guard ring, rather than providing a surge protection element in each cell, it is possible minimize the effect of manufacturing variation (i.e., in-plane variation) on the surge protection function.

A semiconductor device for electrostatic discharge (ESD) protection includes a doped well, a drain region, a source region, a first doped region and a guard ring. The doped well is disposed in a substrate and has a first conductive type. The drain region is disposed in the doped well and has a second conductive type. The source region is disposed in the doped well and has the second conductive type, wherein the source region is separated from the drain region. The doped region is disposed in the doped well between the drain region and the source region, wherein the doped region has the first conductive type and is in contact with the doped well and the source region. The guard ring is disposed in the doped well and has the first conductive type.

An apparatus for suppressing parasitic leakage from I/O pins to substrate in floating rail based ESD protection networks is disclosed. In one embodiment, the apparatus includes an integrated circuit (IC) including a conductor, a pin, a first diode coupled between the pin and the conductor, and a first circuit coupled between the conductor and the pin. The first circuit is configured to selectively couple the pin to the conductor based on a voltage on the pin and a voltage on the conductor.

An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node and a second node. The gate and the body of the discharging transistor are electrically coupled together. The body snatching circuit receives the voltages at the first and second nodes and outputs either the voltage at the first node or the voltage at the second node based on which of these two voltages have a lower value. The output voltage of the body snatching circuit is provided to the body of the discharging transistor.

In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.

A modeling circuit of a field effect transistor includes a first field effect transistor, a first bipolar transistor, a second bipolar transistor and a substrate resistor. The first bipolar transistor has a collector electrode connected to a first node corresponding to a first electrode of the first field effect transistor, an emitter electrode connected to a second node corresponding to a second electrode of the first field effect transistor, and a base electrode. The second bipolar transistor has a collector electrode connected to the second node, an emitter electrode connected to the first node, and a base electrode connected to the base electrode of the first bipolar transistor. The substrate resistor is connected between the base electrodes of the first and second bipolar transistors and a first surface of a semiconductor substrate on which the first field effect transistor is formed.

An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.

An integrated circuit is formed on a substrate, and the integrated circuit includes first and second conductors for providing supply and ground voltages, respectively, a clamp device, and a trigger circuit. The clamp device includes first and second metal oxide semiconductor (MOS) transistors coupled in series between the first and second conductors, wherein the first and second MOS transistors include first and second gates, respectively. The trigger circuit is coupled between the first and second conductors and is configured to drive the first and second gates with first and second voltages, respectively, in response to an electrostatic discharge (ESD) event. The trigger circuit includes a biasing circuit for generating the first voltage as a function of the supply voltage, a PMOS transistor coupled between the first conductor and the second gate, wherein the PMOS transistors includes a third gate. The trigger circuit also includes a resistive element coupled between the first conductor and the third gate, and a capacitive element coupled between the third gate and the first gate. In one configuration a voltage at the third gate should decrease in response to activation of the second MOS transistor.

An ESD protection semiconductor device includes a substrate. A gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins having a first conductivity type are disposed in the substrate respectively at two sides of the gate set. A first doped fin is disposed in the substrate and positioned in between the source fins and spaced apart from the source fins. The first doped fin comprises a second conductivity type that is complementary to the first conductivity type. A second doped fin is formed in one of the drain fins and isolated from the one of the drain fins by an isolation structure. The second doped fin is electrically connected to the first doped fin.