A processor comprising a processor pipeline comprising one or more execution units configured to execute branch instructions, a branch predictor associated with the processor pipeline and configured to predict a branch instruction outcome, a branch classification unit associated with the processor pipeline and the branch prediction unit. The branch classification unit is configured to, in response to detecting a branch instruction, classify the branch instruction as at least one of the following: a simple branch or a hard-to-predict (HTP) branch, wherein a threshold used for the classification is dynamically adjusted based on a workload of the processor.

The present disclosure provides a semiconductor device that prevents a resistor component connected in series with a base electrode from the electrostatic damage. A semiconductor device includes, a collector layer, which is a first conductivity type semiconductor, a base layer, which is a second conductivity type semiconductor and connected with the collector layer, an emitter layer, which is the first conductivity type semiconductor and connected with the base layer, a first electrode, electrically connected to the base layer, a first resistor component, connected in series with the first electrode in a conductive path connecting the first electrode and the base layer, a second electrode, electrically connected to the emitter layer and the first resistor component; and a protection component, connected to the first electrode in parallel with the first resistor component, wherein the protection component comprises a pair of diodes formed by a pn junction and by a way of making both ends of the conductive path into a same polarity.

A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

A semiconductor device is provided, including a first doped region of a first conductivity type configured as a first terminal of a first diode, a second doped region of a second conductivity type configured as a second terminal of the first diode, wherein the first and second doped regions are coupled to a first voltage terminal; a first well of the first conductivity type surrounding the first and second doped regions in a layout view; a third doped region of the first conductivity type configured as a first terminal, coupled to an input/output pad, of a second diode; and a second well of the second conductivity type surrounding the third doped region in the layout view. The second and third doped regions, the first well, and the second well are configured as a first electrostatic discharge path between the I/O pad and the first voltage terminal.

Integrated chips include a first semiconductor device and a second semiconductor device. The first semiconductor device includes a semiconductor channel, a first-type work function layer formed from a first material on the semiconductor channel, and a second-type work function layer formed from a second material on the first-type work function later layer. The second semiconductor device includes a semiconductor channel, a second-type work function layer formed the second material on the semiconductor channel, and a thickness matching layer formed on the second-type work function layer of the second semiconductor device, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer.

A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

A semiconductor apparatus comprises a semiconductor substrate, a dummy trench section which is formed in a front surface of the semiconductor substrate, and a first front-surface-side electrode which is formed above the front surface of the semiconductor substrate and contains metals, and the dummy trench section has a dummy trench formed in the front surface of the semiconductor substrate, an insulation film formed on an inner wall of the dummy trench, a dummy conductive section formed inside the dummy trench on an inner side than the insulation film, and a protection section having an opening to expose at least a part of the dummy conductive section and covering the insulation film on the front surface of the semiconductor substrate, and the first front-surface-side electrode has a portion formed within the opening of the protection section and contacts with the dummy conductive section.

Methods of forming semiconductor devices include forming vertical semiconductor channels on a bottom source/drain layer in a first-type region and a second-type region. A gate dielectric layer is formed on sidewalls of the vertical semiconductor channels. A first-type work function layer is formed in the first-type region. A second-type work function layer is formed in both the first-type region and the second-type region. A thickness matching layer is formed in the second-type region such that a stack of layers in the first-type region has a same thickness as a stack of layers in the second-type region. Top source/drain regions are formed on a top portion of the vertical channels.

Integrated chips include a first semiconductor device and a second semiconductor device. The first semiconductor device includes a semiconductor channel, a first-type work function layer formed from a first material on the semiconductor channel, and a second-type work function layer formed from a second material on the first-type work function later layer. The second semiconductor device includes a semiconductor channel, a second-type work function layer formed the second material on the semiconductor channel, and a thickness matching layer formed on the second-type work function layer of the second semiconductor device, the thickness matching layer having a thickness roughly equal to a thickness of the first-type work function layer.