A CR snubber element includes a first resistance part, a first capacitance part, a second resistance part, and a second capacitance part. The first capacitance part is connected in series to the first resistance part. The second resistance part is connected in series to the first resistance part and the first capacitance part and the second capacitance part is connected in parallel to the second resistance part. The CR snubber element is configured such that the second resistance part is disconnected when the first capacitance part is short-circuited.

An integrated component may include a multilayer capacitor include a first active termination, a second active termination, at least one ground termination, and a pair of capacitors connected in series between the first active termination and the second active termination. The integrated component may include a discrete varistor comprising a first external varistor termination connected with the first active termination and a second external varistor termination connected with the second active termination of the multilayer capacitor.

A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface, a first electrode opposing the first main surface of the semiconductor substrate, a dielectric layer between the semiconductor substrate and the first electrode, a first resistance control layer on the first electrode, a wiring part on the first resistance control layer, and a second electrode opposing the second main surface of the semiconductor substrate. The first resistance control layer includes a first region that has a first electrical resistivity and that electrically connects the first electrode and the wiring part, and a second region that is aligned with the first region and has a second electrical resistivity higher than the first electrical resistivity of the first region.

A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate in the semiconductor substrate, a first STI structure in the semiconductor substrate and surrounding the first vertical diffusion plate, a second vertical diffusion plate in the semiconductor substrate and surrounding the first STI structure, and an ion well in the semiconductor substrate. The ion well is disposed directly under the first vertical diffusion plate, the first STI structure and the second vertical diffusion plate. The second vertical diffusion plate is electrically coupled to an anode of the capacitor structure. The first vertical diffusion plate is electrically coupled to a cathode of the capacitor structure.

An integrated resistor-capacitor (RC) structure (400) is disclosed. The integrated RC structure includes a vertical capacitor (302,402,306) and a resistive element (308,310) disposed above the capacitor. The integrated RC structure uses a low ohmic substrate (302) to ensure a good ground return path for the capacitor. Further, a resistivity of the substrate is configured such that a top plate (306) of the capacitor provides a reference ground above a predefined frequency. The impedance of the resistive element (308,310) is matched, relative to the reference ground, to a predetermined resistance. As such, the resistance of the resistive element (308,310) can be controlled to provide an impedance controlled RC structure over a range of operating frequencies.

A semiconductor device that includes a semiconductor substrate; a first capacitance section on the semiconductor substrate, the first capacitance section including a first electrode layer, a first dielectric layer, and a second electrode layer; a second capacitance section on the semiconductor substrate, the second capacitance section including a third electrode layer, a second dielectric layer, and a fourth electrode layer; a first external electrode; a second external electrode; a first lead wire led out from the first capacitance section to the first external electrode and having an inductance L.sub.1; and a second lead wire led out from the second capacitance section to the second external electrode and having an inductance L.sub.2, wherein an electrostatic capacity C.sub.1 of the first capacitance section and an electrostatic capacity C.sub.2 of the second capacitance section are different, and L.sub.1/L.sub.2=0.8 to 1.2.

In accordance with at least one embodiment, an ESD device comprises: a semiconductor; a pad; a ground rail; a p-well formed in the semiconductor; a first p-type region formed in the p-well and electrically coupled to the ground rail; a first n-type region formed in the p-well and electrically coupled to the pad; a second n-type region formed in the p-well and electrically coupled to the ground rail; an n-well formed in the semiconductor; a first n-type region formed in the n-well; a first p-type region formed in the n-well and electrically coupled to the pad; and a second p-type region formed in the n-well and electrically coupled to the first n-type region formed in the n-well.

A semiconductor package assembly comprising a semiconductor structure (e.g., IC chip) and a package substrate electrically connected to the semiconductor structure is provided. The assembly also comprises a ceramic capacitor that contains alternating dielectric layers and internal electrode layers, the internal electrode layers containing first internal electrode layers and second internal electrode layers. The capacitor further contains external terminals that are disposed on a first surface of the capacitor and electrically connected to the semiconductor structure and external terminals disposed on the second surface of the capacitor that are electrically connected to the package substrate.

A microelectronic assembly comprising a semiconductor structure (e.g., IC chip), an interposer electrically connected to the semiconductor structure, and a package substrate electrically connected to the interposer is provided. The assembly also comprises a decoupling capacitor that contains alternating dielectric layers and internal electrode layers, the internal electrode layers containing first internal electrode layers and second internal electrode layers. The capacitor further contains external terminals that are disposed on a first surface of the capacitor and electrically connected to the package substrate and external terminals disposed on the second surface of the capacitor that are electrically connected to a circuit board.

The present disclosure provides a method for forming a conductive via, and belongs to the technical field of electronic elements. The present method includes: preparing a dielectric layer, and forming a connection via, which extends through the dielectric layer in a thickness direction of the dielectric layer, in the dielectric layer; wherein the dielectric layer includes a first surface and a second surface oppositely arranged in the thickness direction of the dielectric layer; forming a connection electrode in the connection via, forming a first extraction electrode on the first surface, and forming a second extraction electrode on the second surface; wherein the connection electrode at least covers an inner wall of the connection via, and the first extraction electrode and the second extraction electrode are electrically connected to the connection electrode.