A Schottky barrier diode according to an exemplary embodiment of the present disclosure includes: an n− type layer disposed on a first surface of an n+ type silicon carbide substrate; a p+ type region and a p type region disposed on the n− type layer and separated from each other; an anode disposed on the n− type layer, the p+ type region, and the p type region; and a cathode disposed on a second surface of the n+ type silicon carbide substrate, wherein the p type region is in plural, has a hexagonal shape on the plane, and is arranged in a matrix shape, and the n− type layer disposed between the p+ type region and the p type region has a hexagonal shape on the plane and encloses the p type region.

A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region is disposed in the first well. The second well with a second conductive type is disposed adjacent to the first well in a substrate, and the drain region is disposed in the second well. Two gate structures are disposed on the substrate between the source region and the drain region. At least one doping region with the first conductive type is disposed in the second well between the two gate structures.

A semiconductor device includes a semiconductor layer, an electronic element and laterally separated trench isolation structures. The semiconductor layer includes an element region having an inner region, an outer region on opposite sides of the inner region, and a transition region that laterally separates the inner region and the outer region. The electronic element includes a first doped region formed in the inner region and a second doped region formed in the outer region. The trench isolation structures are formed at least in the transition region. Each trench isolation structure extends from a first surface of the semiconductor layer into the semiconductor layer.

A terminal structure of a power device includes a substrate and a plurality of field limiting rings disposed on a first surface of the substrate. The substrate includes a drift layer and a doped layer. The doped layer is formed through diffusion inward from the first surface of the substrate. The doped layer and the drift layer are a first conductivity type, and an impurity concentration of the doped layer is greater than an impurity concentration of the drift layer. The field limiting rings are a second conductivity type. In the terminal structure, lateral diffusion of impurities in the field limiting rings is limited through a design of the doped layer.

The present disclosure has an object of providing a silicon carbide semiconductor device with high productivity which prevents characteristic degradation occurring when a large current is applied to a body diode. A structure including a SiC substrate, a buffer layer, and a drift layer is classified into an active region through which a current flows with application of a voltage to the SiC-MOSFET, and a breakdown voltage support region around a periphery of the active region in a plan view. The active region is classified into a first active region in a center portion, and a second active region between the first active region and the breakdown voltage support region in the plan view. Lifetimes of minority carriers in the second active region and the breakdown voltage support region are shorter than that in the first active region.

A cell structure of a silicon carbide MOSFET device, comprising a drift region (3) located on a substrate layer (2), a second conducting type well region (4) and a first JFET region (51) that are located in the drift region (3), an enhancement region located within a surface of the well region (4), a gate insulating layer (8) located on a first conducting type enhancement region (6), the well region (4) and the first JFET region (51) and being in contact therewith at the same time, a gate (9) located on the gate insulating layer, source metal (10) located on the enhancement region, Schottky metal (11) located on a second conducting type enhancement region (7) and the drift region (3), a second JFET region (52) located on a surface of the drift region (3) between the Schottky metals (11), and drain metal (12).

A semiconductor device includes first and second trenches, and a first layer provided therebetween, in a principal surface of a semiconductor substrate, a second layer in contact with and sandwiching the first trench with the first layer, a third layer provided under the second layer and in contact with the second layer and the first trench, a fourth layer provided under and in contact with the third layer but separated from the first trench, and a fifth layer provided in the principal surface and sandwiching the second trench with the first layer. The second and fourth layers are semiconductors of a first conductivity type, and the first, third, and fifth layers are semiconductors of a second conductivity type. A gate trench electrode is provided inside the first trench via the insulating film, and an emitter trench electrode is provided inside the second trench via the insulating film.

A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.

A power semiconductor device includes a semiconductor layer, a ladder-shaped trench recessed a specific depth from a surface of the semiconductor layer into the semiconductor layer and including a pair of lines having a first depth and a plurality of connectors connected between the pair of lines and having a second depth shallower than the first depth, a well region defined in the semiconductor layer between the pair of lines and between the plurality of connectors of the trench, a floating region defined in the semiconductor layer outside the pair of lines of the trench, a gate insulating layer disposed on an inner wall of the trench, and a gate electrode layer disposed on the gate insulating layer to fill the trench and including a first portion in which the pair of lines is filled and a second portion in which the plurality of connectors is filled. A depth of the second portion of the gate electrode layer is shallower than a depth of the first portion of the gate electrode layer.

A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate is provided. The semiconductor substrate includes a transistor region in which a transistor is formed and a diode region in which a diode is formed. At least one first electrode on a second main surface side of the transistor region and at least one second electrode on a second main surface side of the diode region are made of different materials.