A power semiconductor device includes a control cell for controlling a load current. The control cell is electrically connected to a load terminal structure on one side and to a drift region on another side. The drift region includes dopants of a first conductivity type. The control cell includes: a mesa extending along a vertical direction and including: a contact region having dopants of the first conductivity type or of a second conductivity type and electrically connected to the load terminal structure, and a channel region coupled to the drift region; a control electrode configured to induce a conduction channel in the channel region; and a contact plug including a doped semiconductive material and arranged in contact with the contact region. An electrical connection between the contact region and load terminal structure is established by the contact plug, a portion of which projects beyond lateral boundaries of the mesa.

The semiconductor device configures a cascode-type high voltage element comprising a plurality of low voltage elements connected in series, wherein the number of stages of connected low voltage elements is reduced, and the high voltage element has desired withstand voltage, without limiting the withstand voltage of the gate oxide film of the low voltage elements. The semiconductor device comprises a first semiconductor element and one or more second semiconductor elements connected in series, wherein the first and the second semiconductor elements have a control signal output terminal between a source terminal and a drain terminal or between an emitter terminal and a collector terminal; and a gate terminal of the one or more second semiconductor elements is connected to the control signal output terminal of the first or second semiconductor element connected in series adjacently to the source or emitter side of said one or more second semiconductor elements.

A semiconductor device manufacturing method includes forming a first trench insulating film of a first depth in a substrate, forming at least one second trench insulating film that is spaced apart from the first trench insulating film and has a second depth that is greater than the first depth, forming a body region of a first conductivity type and a drift region of a second conductivity type in the substrate, forming a gate electrode overlapping the first trench insulating film, forming a source region in the body region and a drain region in the drift region, forming a silicide film on the drain region, and forming a non-silicide film between the first trench insulating film and the drain region, wherein the first trench insulating film overlaps the drift region and the gate electrode.

A semiconductor device includes a source/drain diffusion area, a first doped region and a gate. The source/drain diffusion area, defined between a first isolation structure and a second isolation structure, includes a source region, a drain region and a device channel. The first doped region, disposed along a first junction between the device channel and the first isolation structure, is separated from at least one of the source region and the drain region. The first doped region has a dopant concentration higher than that of the device channel. The gate is disposed over the source/drain diffusion area. The first doped region is located within a projected area of the gate onto the source/drain diffusion area, the first isolation structure and the second isolation structure. A length of the first doped region is shorter than a length of the gate in a direction from the source region to the drain region.

A semiconductor device includes a deep well region located on a substrate, a drift region located in the deep well region, a first gate electrode that overlaps with the first body region and the drift region, a second gate electrode that overlaps with the second body region and the drift region, a first source region and a second source region located in the first and second body regions, respectively, a drain region located in the drift region and disposed between the first gate electrode and the second gate electrode, a silicide layer located on the substrate, a first non-silicide layer located between the drain region and the first gate electrode, wherein the first non-silicide layer extends over a top surface of the first gate electrode, and a first field plate contact plug in contact with the first non-silicide layer.

A semiconductor device includes a first common source/drain and a second common source/drain spaced apart from each other in a first direction; a first channel structure between the first common source/drain and the second common source/drain, and a second channel structure between the first common source/drain and the second common source/drain and spaced apart from the first channel structure in a vertical direction; a first gate structure surrounding an upper surface, a lower surface, and side surfaces of the first channel structure; and a second gate structure surrounding an upper surface, a lower surface, and side surfaces of the second channel structure, and spaced apart from the first gate structure, wherein a level of the second channel structure is higher than a level of the first channel structure.

A tub of a semiconductor device includes a cool zone with a first projected operating temperature and a hot zone with a second projected operating temperature greater than the first projected operating temperature. A design parameter has a first value in the cool zone and a second value different from the first value in the hot zone. The difference configures the tub to dissipate less heat in the hot zone during operation of the semiconductor device than would be dissipated if the first and second values were equal. The design parameter may be, for example, a tub width, a source structure width, a JFET region width, a channel length, a channel width, a length of a gate, a displacement of a center of the gate relative to a center of a JFET region, a dopant concentration, or a combination thereof.

A silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a drift region being a first-conductivity type, a body region being a second-conductivity type and provided on the drift region, a source region being the first-conductivity type and provided on the body region such that the source region is separated from the drift region, a contact region being the second-conductivity type and provided on the body region. Gate trenches are provided in the first main surface, and extend in a first direction parallel to the first main surface. The contact region is in contact with a first gate trench from both sides in a second direction orthogonal to the first direction and spaced apart from a second gate trench adjacent to the first gate trench in the second direction.

A power semiconductor device includes a control cell for controlling a load current and electrically connected to a load terminal structure on one side and to a drift region on another side. The drift region includes dopants of a first conductivity type. The control cell includes: a mesa extending along a vertical direction and including a contact region having dopants of the first or second conductivity type and electrically connected to the load terminal structure, and a channel region coupled to the drift region; a control electrode configured to control a conduction channel in the channel region; and a contact plug including at least one of a doped semiconductive material or metal, and arranged in contact with the contact region. An electrical connection between the contact region and load terminal structure is established by the contact plug, a portion of which horizontally projects beyond lateral boundaries of the mesa.

A semiconductor device of an embodiment includes an electrode; and a silicon carbide layer in contact with the electrode and including: a first silicon carbide region of n-type; and a second silicon carbide region disposed between the first silicon carbide region and the electrode, in contact with the electrode, and containing at least one oxygen atom bonded to four carbon atoms.