Operating a PNP double-sided double-base bipolar junction transistor (DSDB BJT). One example is a method of operating a DSDB-BJT, the method comprising: conducting a first load current from an upper terminal of the power module to an upper base of the transistor, through the transistor, and from a lower base to a lower terminal of the power module; and then responsive assertion of a first interrupt signal interrupting the first load current from the lower base to the lower terminal by opening a lower-main FET and commutating a first shutoff current through a lower collector-emitter of the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.

The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the B-TRAN type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

A semiconductor device and its manufacturing method are presented. The semiconductor device includes a collection region, a base region adjacent to the collection region, an emission region adjacent to the base region, and a doped semiconductor layer on the emission region. The width of the doped semiconductor layer is larger than the width of the emission region, a conductive type (e.g., P-type or N-type) of the doped semiconductor layer is the same as a conductive type of the emission region. In this inventive concept, the width of the doped semiconductor layer on the emission region is larger than the width of the emission region, that equivalently increases the width of the emission region, which in turn increases the DC amplification factor () and therefore improves the overall performance of the semiconductor device.

Thin bidirectional bipolar junction transistor (BJT) devices and methods for fabricating thin bidirectional BJT devices. The method includes forming a first base region and a first emitter/collector region on a first side of a first thick semiconductor wafer. The method also includes removing a portion of the first thick semiconductor wafer to produce a first thin semiconductor wafer. The method further includes forming a second base region and a second emitter/collector region on a second side of the first thin semiconductor wafer opposite the first side. The method also includes producing a second thin semiconductor wafer. The method further includes bonding the first thin semiconductor wafer to the second thin semiconductor wafer.

Embodiments herein describe a through-substrate via formed in a semiconductor substrate that includes a transistor. In one embodiment, the through-substrate via includes a BJT which includes different doped semiconductor layers that form a collector, a base, and an emitter. The through-substrate via can also include metal contacts to the collector, base, and emitter which enable the through-substrate via to be coupled to a metal routing layer or a solder bump.

Methods and systems for operating a double-base bidirectional power bipolar transistor. Two timing phases are used to transition into turn-off: one where each base is shorted to its nearest emitter/collector region, and a second one where negative drive is applied to the emitter-side base to reduce the minority carrier population in the bulk substrate. A diode prevents reverse turn-on while negative base drive is being applied.

Double sided versions of several power transistor types are devices that are already known in the literature. Devices built in this configuration are generally required to have a separate driver circuit to control the front and rear control electrodes and provide the gate or base voltage and/or currents for the power switch. This is because there may be of the order of 1000V potential-difference between the frontside and rearside potentials when the transistor is in the off conditionand a single integrated circuit cannot generally sustain this within a single package. The NPN configuration is preferred in this case to benefit from electron conduction for the main power path between the emitters. However, problems arising when using a P-type wafer. The present invention seeks to avoid the use of P-type wafers while still getting the higher conduction performance of NPN operation.

Embodiments herein describe a through-substrate via formed in a semiconductor substrate that includes a transistor. In one embodiment, the through via includes a BJT which includes different doped semiconductor layers that form a collector, a base, and an emitter. The through via can also include metal contacts to the collector, base, and emitter which enable the through to be coupled to a metal routing layer or a solder bump.

Embodiments herein describe a through-substrate via formed in a semiconductor substrate that includes a transistor. In one embodiment, the through via includes a BJT which includes different doped semiconductor layers that form a collector, a base, and an emitter. The through via can also include metal contacts to the collector, base, and emitter which enable the through to be coupled to a metal routing layer or a solder bump.

Embodiments herein describe a through-substrate via formed in a semiconductor substrate that includes a transistor. In one embodiment, the through-substrate via includes a BJT which includes different doped semiconductor layers that form a collector, a base, and an emitter. The through-substrate via can also include metal contacts to the collector, base, and emitter which enable the through-substrate via to be coupled to a metal routing layer or a solder bump.