A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a patterned mask on the buffer layer; using the patterned mask to remove the buffer layer for forming ridges and a damaged layer on the ridges; removing the damaged layer; forming a barrier layer on the ridges; and forming a p-type semiconductor layer on the barrier layer.

A semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a group of negatively-charged ions, and a field plate. The gate electrode and the drain electrode disposed above the second nitride-based semiconductor layer to define a drift region therebetween. The group of negatively-charged ions are implanted into the drift region and spaced apart from an area directly beneath the gate and drain electrodes to form at least one high resistivity zone in the second nitride-based semiconductor layer. The field plate is disposed over the gate electrode and extends in a region between the gate electrode and the high resistivity zone.

A semiconductor device 1 has an electrode structure that includes source electrodes 3, a gate electrode 4, and drain electrodes 5 disposed on a semiconductor laminated structure 2 and extending in parallel to each other and in a predetermined first direction and a wiring structure that includes source wirings 9, drain wirings 10, and gate wirings 11 disposed on the electrode structure and extending in parallel to each other and in a second direction orthogonal to the first direction. The source wirings 9, the drain wirings 10, and the gate wirings 11 are electrically connected to the source electrodes 3, the drain electrodes 5, and the gate electrode 4, respectively. The semiconductor device 1 includes a conductive film 8 disposed between the gate electrode 4 and the drain wirings 10 and being electrically connected to the source electrodes 3.

Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.

There is provided a semiconductor layer structure (100) comprising: a Si substrate (102) having a top surface (104); a first semiconductor layer (110) arranged on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures (112) arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN; a second semiconductor layer (120) arranged on said first semiconductor layer laterally and vertically enclosing said nanowire structures, the second semiconductor layer comprising Al.sub.xGa.sub.1-xN, wherein 0≤x≤0.95; a third semiconductor layer (130) arranged on said second semiconductor layer, the third semiconductor layer comprising Al.sub.yGa.sub.1-yN, wherein 0≤y≤0.95; and a fourth semiconductor layer (140) arranged on said third semiconductor layer, the fourth semiconductor layer comprising GaN. There is also provided a high-electron-mobility transistor device and methods of producing such structures and devices.

This disclosure describes the structure of a transistor that provides improved performance by reducing the off-state capacitance between the source and the drain by using a cap layer to extend the electrical distance between the gate and the source and drain contacts. In certain embodiments, a dielectric layer may be disposed between the gate electrode and the cap layer and vias are created in the dielectric layer to allow the gate electrode to contact the cap layer at select locations. In some embodiments, the gate electrode is offset from the cap layer to allow a more narrow cap layer and to allow additional space between the gate electrode and the drain contact facilitating the inclusion of a field plate. The gate electrode may be configured to only contact a portion of the cap layer.

Methods for manufacturing double-slanted gate connected field plates that allow for the simultaneous optimization of electric field distributions between gate and drain terminals and gate and source terminals are described. A technical benefit of manufacturing the double-slanted gate connected field plate using greyscale lithography is that fabrication costs may be substantially reduced by reducing the number of process steps required to form the double-slanted gate connected field plate. The source-side slope and the drain-side slope of the double-slanted gate connected field plate may be concurrently formed with two different slopes or two different step profiles.

A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation and the mesa structure. The mesa structure includes a channel layer and a barrier layer disposed on the channel layer. The contact structure includes a body portion and a plurality of protruding portions. The body portion is through the passivation layer. The protruding portions connect to a bottom surface of the body portion and through the barrier layer and a portion of the channel layer.

A high-electron mobility transistor includes a substrate; a channel layer on the substrate; a AlGaN layer on the channel layer; and a P—GaN gate on the AlGaN layer. The AlGaN layer comprises a first region and a second region. The first region has a composition that is different from that of the second region.

A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.