A bipolar transistor includes a first PN junction and a second PN junction. A first gate is located on the first PN junction. A second gate is located on the second PN junction.

Provided is a lateral insulated-gate bipolar transistor (LIGBT), comprising a substrate (10), an anode terminal and a cathode terminal on the substrate (10), and a drift region (30) and a gate (61) located between the anode terminal and the cathode terminal. The anode terminal comprises a P-type buried layer (52) on the substrate (10), an N-type buffer region (54) on the P-type buried layer (52), and a P+ collector region (56) on the surface of the N-type buffer region (54). The LIGBT further comprises a trench gate adjacent to the anode terminal, wherein the trench gate penetrates from the surfaces of the N-type buffer region (54) and the P+ collector region (56) to the P-type buried layer (52), and the trench gate comprises an oxidation layer (51) on the inner surface of a trench and polysilicon (53) filled into the oxidation layer.

A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers.

The present invention relates to a lateral high-voltage device. The device includes a dielectric trench region. A doping-overlapping structure with different doping types alternating mode is provided at least below, on a left side of, or on a right side of the dielectric trench region. The device also includes a dielectric layer, a body field plate, a polysilicon gate, a gate oxide layer, a first N-type heavy doping region, a second N-type heavy doping region, a P-type heavy doping region, a P-well region, the first N-type doping pillar, the second N-type doping pillar, the third N-type doping pillar, the first P-type doping pillar, and the second P-type doping pillar. The invention adopts a dielectric trench region in the drift region to keep the breakdown voltage BV of the device while reducing the surface area of the device, and effectively reducing the device's specific On-Resistance R.sub.ON,sp.

Circuit configurations and related methods are provided that may be implemented using insulated-gate bipolar transistor (IGBT) device circuitry to protect at risk circuitry (e.g., such as high voltage output buffer circuitry or any other circuitry subject to undesirable ESD events) from damage due to ESD events that may occur during system assembly. The magnitude of the trigger voltage V.sub.T1 threshold for an IGBT ESD protection device may be dynamically controlled between at least two different values so that trigger voltage V.sub.T1 threshold for an IGBT ESD protection device may be selectively reduced when needed to better enable ESD operation.

An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.

A display substrate is provided. The display substrate includes a gate electrode disposed on a base; a gate insulating layer disposed on the base and covering the gate electrode; a semiconductor layer disposed on the gate insulating layer and overlapping the gate electrode; a source electrode and a drain electrode disposed on the semiconductor layer and connected to the semiconductor layer; a pixel electrode disposed on the gate insulating layer, connected to the drain electrode, and extending from the drain electrode; a common electrode insulated from the pixel electrode and overlapping the pixel electrode; and a semiconductor pattern disposed between the gate insulating layer and the pixel electrode, the semiconductor pattern overlapping the pixel electrode. The semiconductor pattern comprises a same material as the semiconductor layer and extends from the semiconductor layer.

A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration.

The present invention relates to an integrated cylindrical power cell module and a manufacturing method thereof, and belongs to the field of power cells. The cylindrical cells in the present invention are placed in the mounting holes corresponding to each other one by one on a first housing and a second housing, and both poles of the cylindrical cell are respectively fitted on heat management modules by a heat-conducting adhesive. In this way, the cylindrical cell is light in weight, low in cost, and good in sealing performance and also in heat dissipation. Temperature acquisition modules are provided on a cylindrical surface and two poles of the cylindrical cell to coordinate with the heat management modules, allowing the cylindrical cell to have a better operating temperature. Conical guideposts surrounding the mounting holes are provided around the mounting holes.

Composite substrates for use in semiconductor switching devices, including insulated gate bipolar transistors (IGBT), switching devices formed therewith, and methods of use. The composite substrate includes a nano-scale graphene film on a sapphire-containing surface of a dielectric substrate, wherein the nano-scale graphene film and sapphire-containing surface exhibit lattice alignment properties capable of improving thermal performance of the switching device and reducing local temperature hotspots in the switching device.